setuphold notifier
This is the verilog file from the tsmc library
`timescale 1ns/1ps
`celldefine
module SDFFNRX2 (Q, QN, D, SI, SE, CKN, RN);
output Q, QN;
input D, SI, SE, CKN, RN;
reg NOTIFIER;
supply1 xSN;
supply1 dSN;
buf XX0 (xRN, RN);
not IC (clk, CKN);
udp_dff I0 (n0, n1, clk, xRN, xSN, NOTIFIER);
udp_mux I1 (n1, D, SI, SE);
buf I2 (Q, n0);
not I3 (QN, n0);
and I4 (SandR, xSN, xRN);
and I5 (SandRandSE, SandR, SE);
not I6 (SEb, SE);
and I7 (SandRandSEb, SandR, SEb);
xor I8 (DxorSD, D, SI);
and I9 (flag, DxorSD, SandR);
specify
specparam
tplh$RN$Q = 1.0,
tphl$RN$Q = 1.0,
tplh$RN$QN = 1.0,
tphl$RN$QN = 1.0,
tminpwl$RN = 1.0,
tminpwh$RN = 1.0,
tsetup$RN$CKN = 1.0,
thold$RN$CKN = 0.5,
tplh$CKN$Q = 1.0,
tphl$CKN$Q = 1.0,
tplh$CKN$QN = 1.0,
tphl$CKN$QN = 1.0,
tsetup$D$CKN = 1.0,
thold$D$CKN = 0.5,
tsetup$SI$CKN = 1.0,
thold$SI$CKN = 0.5,
tsetup$SE$CKN = 1.0,
thold$SE$CKN = 0.5,
tminpwl$CKN = 1.0,
tminpwh$CKN = 1.0;
// path delays
if (SandRandSEb)
(negedge CKN *> (Q +: D)) = (tplh$CKN$Q, tphl$CKN$Q);
if (SandRandSE)
(negedge CKN *> (Q +: SI)) = (tplh$CKN$Q, tphl$CKN$Q);
( negedge RN *> (Q +:1'b0) ) = (tplh$RN$Q, tphl$RN$Q );
if (SandRandSEb)
(negedge CKN *> (QN -: D)) = (tplh$CKN$QN, tphl$CKN$QN);
if (SandRandSE)
(negedge CKN *> (QN -: SI)) = (tplh$CKN$QN, tphl$CKN$QN);
( negedge RN *> (QN -:1'b0) ) = (tplh$RN$QN, tphl$RN$QN );
// timing checks
$setuphold(negedge CKN &&& (SandRandSEb == 1), posedge D, tsetup$D$CKN ,thold$D$CKN , NOTIFIER);
$setuphold(negedge CKN &&& (SandRandSEb == 1), negedge D, tsetup$D$CKN ,thold$D$CKN , NOTIFIER);
$setuphold(negedge CKN &&& (SandRandSE == 1), posedge SI, tsetup$SI$CKN ,thold$SI$CKN , NOTIFIER);
$setuphold(negedge CKN &&& (SandRandSE == 1), negedge SI, tsetup$SI$CKN ,thold$SI$CKN , NOTIFIER);
$setuphold(negedge CKN &&& (flag == 1), posedge SE, tsetup$SE$CKN ,thold$SE$CKN , NOTIFIER);
$setuphold(negedge CKN &&& (flag == 1), negedge SE, tsetup$SE$CKN ,thold$SE$CKN , NOTIFIER);
$width(negedge CKN &&& (SandR == 1), tminpwl$CKN, 0, NOTIFIER);
$width(posedge CKN &&& (SandR == 1), tminpwh$CKN, 0, NOTIFIER);
$setuphold(negedge CKN, posedge RN, tsetup$RN$CKN ,thold$RN$CKN , NOTIFIER);
$width(negedge RN, tminpwl$RN, 0, NOTIFIER);
endspecify
endmodule // SDFFNRX2
`endcelldefine
Any further suggestions?
Thanks