problems in synthesis with DC

Hello all,

I am trying to synthesize gate level logic of my behavior level code(verilog) by design compiler . i am using faraday 130nm library. I have a divided clock derived from a 7 bit counter . I made the network as dont touch (counter) so that synthesizer wont try to optimize and modify it . After synthesis i tried to simulate the gate level netlist on modelsim with the source file of the library and .sdf file .

while simulation modelsim is giving error of Module '\**SEQGEN** ' is not defined.
in the synthesized netlist , this cell is used for forming the counter.

1) what i feel is that i should also specify the standard cell to be used to make the counter network.
*but dont know how to specify that --- command in DC - help in this regard

2) Hard code the counter block structurally. This would be a lengthy affair .
i am just check Dynamic time analysis and and there would be other blocks also in the design whos timing are not met ...

what is general procedure to deal with such problems in synthesis .

kindly help ... i am a newbie in this field

regards
Aimer

First, why don't you want your counter optimized?

Second, Are you sure the design has been mapped to your library? The first thing DC does is translate the RTL to what are called 'GTECH' generic gates. Then it maps from GTECH to your intended library. Open up the netlist and look around inside. If the only thing that hasn't been mapped is your counter, the 'dont touch' may be somehow preventing it from being mapped. If the whole netlist is GTECH cells, something is wrong with your scripts.

1) my counter is of 7 bits and i am deriving clock from each bit (clkby2,clkby4 etc) . When i hadnt kept the counter as dont touch, synthesizer reduced the no. of bits to 5.
thats why i kept it dont touch next time .
2) All other logic blocks are mapped to standard cell library cells except this.
Are u aware of any command by which we can specify the standard cell to be used in dont touch nets !

thanks for ur reply

regards
aimer

try to put dont touch just before compile_ultra,