problems in mixed signal design

[arsenal]

hi,
when i do mixed signal simulation in cadence, some problems occured.
i have compiled some digital .v files using verilog-xl 05.40.003-s, and it finished without errors.
however, when i build a block with behavioral view to be used in config and with the same verilog code, the HDL parser give some errors at such codes as "wire signed", "20'sh00004" and "always @(*)",

so can anyone tell me what to do ?
thanks

 

[sunking]

the result about hdl parser is for ahdl(or verilog-a).
check the open book, it give you a detail about mixed signal simulation.

 

[arsenal]

hi sunking,
you mean candence use the verilog-a hdl parser to compile digital verilog code?
but some of my other verilog files have passed compilation and the symbols have also been generated and now it seems only some problems of syntax error.
it seems hdl parser uses another version of verilog compiler and not the same as the one i use in terminal verilog compilation.