biswaIITH
Full Member level 4
So what is your suggestion now to improve the EMI??as it is too late to change the topology..What measures should i take now to decrease the EMI if not eliminate entirely????
The "free lunch" saying is quite often quoted at Edaboard when talking about design trade-offs.
It this case, it means that the tricky topology most likely involves higher EMI than industry standard PFC designs. There's a reason why commercial PFC power supplies use a different topology.
I just noticed that biswaIITH deleted his post with a circuit schematic before my post #17.
Unfortunately the succeeding discussion becomes more or less meaningless without this information. I didn't save the original pdf, see below my reproduction of the topology. Buck-boost and boost LC-values and switching parameters are for test only. I would appreciate to see the original schematic again.
As briefly mentioned in post #17, the topology is different from standard PFC switchers by using a buck-boost instead of a pure boost PFC stage. Main advantage is that the PFC bus voltage can be below input peak voltage. Simultaneous control of both transistors isn't necessarily involved with this topology, but has been apparently chosen by the OP for simplicity.
BradtheRad has simplified the topology to a buck PFC circuit. It's a valid option, but only reasonable if the output voltage is considerably below input voltage so that you can at least partly achieve a sine input current waveform.
sorry for the inconvenience....could you plzz help me design appropriate EMI filters for it...I am planning to test my general purpose board based circuit using EMI filters before i start designing PCB for it...
The current waveform is probably good enough to comply with PFC regulations. You have the simulation tool to find out why it is as you see it.
If the simulation results are different, your next step could be to approach more realistic model parameters.
The waveform doesn't give an indication of low efficiency. Power factor doesn't lie, if it tells that most of the input current spectral power is concentrated in the fundamental, there won't be excessive losses caused by the current waveform.
But there are other candidates for causing bad efficiency, particularly switching losses. Again you have the simulation to identify possible loopholes in your design. And if real circuit behaviour doesn't confirm the simulation, measurements are necessary. Component temperature is often a good indicator.
You don't necessarily need sophisticated equipment. The first step is to identify possibly loss meachanisms and find out which of it is dominant in your circuit. Besides semiconductor switching losses there are e.g. resistive winding and core losses, the latter possibly promoted by core saturation.
A possible reason for a "peaky" (triangle or worse) waveform could be saturation of the PFC inductor, by the way.
Using a lower inductor value primarly causes higher PWM frequent ripple. Core saturation is a a different thing. Be sure that the inductor is designed for the circuit peak current.
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Needless to say that higher peak current involves increased transistor and diode switching and foward losses also without core saturation?
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