"Problems encountered during simulation" in cadenc

[tshankar501]

problems encountered during simulation

Hi,

I am running mixed signal simulation in spectre-verilog simulator with digital blocks implemented using verilog and analog blocks with transistors in spectre. I have created a 'config' view to simulate it.

When I try to click 'netlist and run' button, the analog and digital netlist are getting generated successfully, but after the creation of netlist, it fails to simulate.

It says that "Problems encountered during simulation".
Use the Simulation -> Output Log menu for more information

When I try to access Output Log, it is greyed out; it is not in selectable mode and so I can't view the output log. Please let me know if anybody encountered this and why is this occuring?

Thanks,
Shankar.T

 

[Teddy]

simulation->output log menu

try to go to you rsimulation directory (where the output data are saved) and look if the ouput log is 0B size. If is not zero you can view it from command line.

 

[tshankar501]

spectre problems encountered during simulation

ya, the output file is 0 Kb. Only the netlist was produced, the simulation just getting started and immediately it is getting stopped with the above message. It is not storing anything into the file.

 

[pvnk]

simulation output log blanked out

hi ther,

i'm facing the same problem. it successfully netlists and prints this same error message. i cant see any output file though. i tried with only analog lib elements ( without using model file ) even in that case this error showed up.

any one solved this before? help us ! ;-)

cheers
pvnk