Problems compiling designs using FPGA Advantage FOR FRAMES.

[gezzas525]

Having trouble compiling a small RAM for my Masters project, iam using the FOR FRAME to create an 8x8 RAM cell.

Heres the problem the design compiles at UNI using FPGA Advantage 5.3, however at home using version 6.2 the generated output is slightly different and the errors are listed below.




** Error: F:/VHDL/MVSD3_ILP/crane/hdl1/ram_struct.vhd(112): near "begin": expecting: END

** Error: F:/VHDL/MVSD3_ILP/crane/hdl1/ram_struct.vhd(116): near "all": expecting: IDENTIFIER







here is the generated out put, i can see nothing wrong with it.







-- VHDL Entity crane.Ram.interface
--
-- Created:
-- by - kleo.UNKNOWN (ZEUS)
-- at - 01:18:04 18/01/2004
--
-- Generated by Mentor Graphics' HDL Designer(TM) 2003.2 (Build 28)
--
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_arith.all;

ENTITY Ram IS
PORT(
Address_H : IN std_logic_vector (7 DOWNTO 0);
MemIn_H : IN std_logic_vector (5 DOWNTO 0);
wr_H : IN std_logic;
MemOut_H : OUT std_logic_vector (5 DOWNTO 0)
);

-- Declarations

END Ram ;

--
-- VHDL Architecture crane.Ram.struct
--
-- Created:
-- by - kleo.UNKNOWN (ZEUS)
-- at - 01:18:04 18/01/2004
--
-- Generated by Mentor Graphics' HDL Designer(TM) 2003.2 (Build 28)
--
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.numeric_std.all;

LIBRARY crane;

ARCHITECTURE struct OF Ram IS

-- Architecture declarations
type mem_array is array(0 to 7) of std_logic_vector(5 downto 0);

-- Internal signal declarations
SIGNAL ColDec : mem_array;
SIGNAL ColDec_L : std_logic_vector(7 DOWNTO 0);
SIGNAL RowDec_L : std_logic_vector(7 DOWNTO 0);


-- Component Declarations
COMPONENT Col_Decoder
PORT (
Wr_H : IN std_logic ;
sel_H : IN std_logic_vector (2 DOWNTO 0);
ColDec_L : OUT std_logic_vector (7 DOWNTO 0)
);
END COMPONENT;
COMPONENT Memory_Cell
PORT (
Csel_L : IN std_logic ;
Rsel_L : IN std_logic ;
D : IN std_logic_vector (5 DOWNTO 0);
Q : OUT std_logic_vector (5 DOWNTO 0)
);
END COMPONENT;
COMPONENT Row_Decorder
PORT (
sel_H : IN std_logic_vector (2 DOWNTO 0);
RowDec_L : OUT std_logic_vector (7 DOWNTO 0)
);
END COMPONENT;

-- Optional embedded configurations
-- pragma synthesis_off
FOR ALL : Col_Decoder USE ENTITY crane.Col_Decoder;
FOR ALL : Row_Decorder USE ENTITY crane.Row_Decorder;
-- pragma synthesis_on


BEGIN
-- Architecture concurrent statements
-- HDL Embedded Text Block 1 MUX_8TO1
-- MUX_8TO1

with Address_H(2 downto 0) select
MemOut_H(5 downto 0) <= ColDec(0) when "000",
ColDec(1) when "001",
ColDec(2) when "010",
ColDec(3) when "011",
ColDec(4) when "100",
ColDec(5) when "101",
ColDec(6) when "110",
ColDec(7) when "111",
(others => 'X') when others;


-- Instance port mappings.
I1 : Col_Decoder
PORT MAP (
Wr_H => wr_H,
sel_H => Address_H(2 DOWNTO 0),
ColDec_L => ColDec_L
);
I2 : Row_Decorder
PORT MAP (
sel_H => Address_H(5 DOWNTO 3),
RowDec_L => RowDec_L
);

g1: FOR j IN 0 TO 7 GENERATE
BEGIN ###1st error
g0: FOR i IN 0 TO 7 GENERATE
-- Optional embedded configurations
-- pragma synthesis_off
FOR ALL : Memory_Cell USE ENTITY crane.Memory_Cell; ###2nd error
-- pragma synthesis_on

BEGIN
I0 : Memory_Cell
PORT MAP (
D=>MemIn_H,
Csel_L=>ColDec_L(j),
Q=>ColDec(j),
Rsel_L=>RowDec_L(i)
);
END GENERATE g0;

END GENERATE g1;

END struct;

 

[elektrom]

Re: Problems compiling designs using FPGA Advantage FOR FRAM

1) Make sure that the "Col_Decoder", "Memory_Cell" and "Row_Decorder" are already compiled and shown in "crane" library.

2) Check VHDL complie option to use 1993 syntax

 

[gezzas525]

Re: Problems compiling designs using FPGA Advantage FOR FRAM

Everything was allready generated and compiled, the VHDL 93 syntax option WORKED the design now compiles correctly. But in FPGA 5.3 that option is turned off.

1) what does VHDL 93 syntax mean/do to the design.
2) why does the design compile in FPGA 5.3 with the option turned off, and does not compile in 6.2. Did Mentor change something major in the software.


help much appreciated I can now continue with my design after sorting out this stumbling block.

elektrom you know your stuff

KLEO