Problems about pixel photodiode layout

Hello, I'm doing the doing the pixel photodiode layout for the first time. It's a pinned-photodiode(p-sub/n-well/p+)
Should I fully cover the n-well region by ACT(active region) in layout? There are DRC and LVS errors if I do this, and if I only cover the p+ region(enclosed by n-well) with ACT, then DRC and LVS is OK but non-ACT regions will become STI in the photodiode which is not expected.
Anyone who has an idea? or other advice on this layout? Thanks alot!

DRC error:
1. ACT must be fully covered by NPLUS or PPLUS
LVS error:
1. The 2 contacts (one from p+ and the other from n+ in n-well) is regarded as shorted because they are located in the same ACT.
(BUT I'm using large ACT region only to define a non-STI region for photodiode, and from the cross-section, they shouldn't be shorted at all)

Your attachment is "invalid", e.g. cannot be presented.

Are your contacts p+ in p diffusion (in nwell), and n+ in n(well) diffusion?

From what I've seen, if you want to do a good job on
imager design in a non-imager-optimized process you
will probably have to break some rules and it may take
a few iterations to decide which ones.

Things like having poor quality oxides abutting the
depletion region give rise to excess noise (RTN is
a real nuisance because it's unfilterable). Field plates
and buried junctions are used to push the depletion
region away from such nastiness, but these are
"CMOS-abnormal" and might well flag in a vanilla
CMOS foundry DRC deck.

Amyway, if this is your deal, maybe you want to start
with a likely-looking cross section, figure out how to
make it so, and negotiate waivers when you're sure
there's nothing but "foundry unexpectedness" left in
the error-pile.

erikl said:

Your attachment is "invalid", e.g. cannot be presented.

Are your contacts p+ in p diffusion (in nwell), and n+ in n(well) diffusion?

Click to expand...

Yes.

The figure is uploaded again:

Thank you,
An extra question is that, we found a "thick oxide(like TGO)" layer in both of our 2 reference pixel photodiode designs, so what's the role of this layer? Does it make the pixel perform better?

It's a better quality oxide than field ox, so can help
with the noise effects. What's over it (e.g. if poly,
it may be acting as a field plate?) might be illuminating
(heh).

But why thick oxide? I mean the normally used thin oxide for MOSFETs is good quality as well. Thick oxide is found in high-V IO devices and we are not sure about the effect of it in pixels.

I expect it's not -that- much thicker and its interface
qualities should be similar (unlike field oxide). The thick
gate ox will push the first ILD layer that much further
away from the interface (maybe this matters, maybe it
does not). Without looking at things like poly, can't say
whether there's a voltage related reason.

Re: DRC and LVS errors

erikl said:

Are your contacts p+ in p diffusion (in nwell), and n+ in n(well) diffusion?

Click to expand...

czq1419 said:

Yes.

View attachment 100383

Click to expand...

From your figure I can't recognize if there's a p diffusion below the p+ contact. It's a must! The size of this p diffusion represents the actual size of the photo diode (at least for fast action).