Hi,
You are using "Master parallel interface".
* datasheet says to drive RD continously low. But in your diagram it is toggeling.
You say you read data by rising edge of busy. But rising edge shows the beginning of a conversion...not the end of a conversion.
Busy is active during two conversions. First A then B.
As far as i can see: You may read the first conversion result on the first falling edge of EOC, the next conversion result either on the next falling edge of EOC, or the falling edge of Busy.
Looking in the datasheet it really is a bit weird.
Especially the description of the data on the databus. Either A or B. It is important to know what data there is.
If it is controlled by the A/B signal, then they should show this, but it seems it is changing randomly.
Try this:
* RD continously low
* read conversion result A on the first falling edge of EOC (after conversion start)
* read conversion result B on falling edge of Busy.
For further discussion it may be useful to post your FPGA code.
Klaus