problem_with_AD7655ADC

[STU_KNTU]

hi guys.
i am using AD7655 4channel Analog to digital converter to convert TCD_Linear signal with Fpga.
but i have some problem.
fpga gives to ADC a Cnvst clock with 400 khz frequency and ADC gives to fpga a busy signal(time for converting signal.i am reading data from ADC in raising edge of busy.
but data pins (D0 to D15) are very invalid and their voltage is variable!!!some times 1v and some times 3.3v!
is there possibility that ADC got Burnt??i mean the eoc pin and busy pin are correct but not Data pins.
if ADC is good so is there possibility that i am reading data in bad times???
i am using it in 1 channel INA1.

 

[KlausST]

Hi,

How can we know.
You should give us useful informations, not emotions.

We need to know the curcuit. The hardware.
It begins with the complete ADC circuit. Analog input to digital output.
Then we need to know the signals and their timings.
And then we need to see the digital data, the conversion results.

In short: facts. Complete facts.

Then I am sure we can help you.

Klaus

 

[STU_KNTU]

thanks for your response.
about timing diagram i sample analog data with 400 khz frequency (Cnvst = 400 khz)
and read data in raising edge or falling edge of bust.(not different).
the data's i receive is very interesting!! the 8bit lsb for all numbers is same.
in 8 bit msb difference is in D14 and D15. some times '11' or '10' or '01' and ...
one other point is when i was soldering the chip the AGND pin0 was disconnected of the chip! but i have tested it and it was connect to other GNDs in inside of chip.
the data is coming from CCD_Linear sensor and i buffered it with AD 8021 low noise op amp.

 

[KlausST]

Hi,

We only are able to help if we have the requested informations of post#2.


Klaus

 

[STU_KNTU]

schematic circuit for ADC,Vref and Opamp:

 

[STU_KNTU]

and my wave form test.
i am reading datA in yellow line.

 

[KlausST]

Hi,

Soem issues to your timing diagram:
* conversion clock is far away from 400kHz
* on a falling edge of CNVST the ADC reacts with a rising edge of the busy signal.
* RD signal should be idle high and clocks in data on the rising edge.

please provide correct data.

Klaus

 

[STU_KNTU]

hi klaus.
First excuses for the delay in answering.

* RD signal should be idle high and clocks in data on the rising edge.

are you sure??
I'm set Rd and Cs low according to data sheet.
please take a look to this :

* conversion clock is far away from 400kHz
* on a falling edge of CNVST the ADC reacts with a rising edge of the busy signal.

yes i see you're right.but it doesn't affect the correctness of ADC Reading process.
the error happened because i hadn't oscope to take right picture.
here is main timing diagram :

1.i'm reading data in raising edge of busy.
2.Cnvst frequency is about 50 khz in this timing diagram.

 

[KlausST]

Hi,

You are using "Master parallel interface".
* datasheet says to drive RD continously low. But in your diagram it is toggeling.

You say you read data by rising edge of busy. But rising edge shows the beginning of a conversion...not the end of a conversion.
Busy is active during two conversions. First A then B.
As far as i can see: You may read the first conversion result on the first falling edge of EOC, the next conversion result either on the next falling edge of EOC, or the falling edge of Busy.

Looking in the datasheet it really is a bit weird.
Especially the description of the data on the databus. Either A or B. It is important to know what data there is.
If it is controlled by the A/B signal, then they should show this, but it seems it is changing randomly.

Try this:
* RD continously low
* read conversion result A on the first falling edge of EOC (after conversion start)
* read conversion result B on falling edge of Busy.

For further discussion it may be useful to post your FPGA code.

Klaus

 

[STU_KNTU]

thanks alot.
i will post my fpga code but before that :is there any problem with my schematic circuit???
especially in Vref,i saw in analog device that i should use a 47uf capacitor parallel with Vref. but i dont.
what do you think about that???
thanks again for your response...

 

[FvM]

Purpose of Vref bypassing is explained in the datasheet. A 47 µF capacitor is suggested for full ADC performance, operation with smaller capacitance is surely possible. It looks like you have no Vref bypass at all, which is probably no good idea.

I also notice that you are supplying AD829 with single 5V, outside the specified range. The ADC voltage range will be at least cut down from 0..5 V to about 1.5..3.5 V only.

 

[KlausST]

Hi,

You recognized the wrong naming of pins 19/40/41 of the symbol. It is confusing.

I recommend to use capacitors, at least a 100nF ceramic next to the Ref pins. Often the ADCs draw pulsed currents on the ref pin and usually the voltage reference is not fast enough to regulate the pulses. It needs to be well damped and stable regulated. Maybe aseries resistor may improve this. Try 10 ohms.

Use fast ceramic capacitors at each supply pin and at least one bulk capacitor.

Don't leave the analog inputs floating, (the same with digital inputs).
( I once had and multichannel ADC with one analog input floating, it caused the conversion on all other channels to fail)

Klaus

 

[STU_KNTU]

with connecting float pins(such as other channels) to GND and Using a 1 UF capacitor for ref pin i got my result and data became true!!never ever leave other channels unconnected!!!!!
special thanks to KlausST and FvM.
:smile: