Problem with VHDL synthesis of a big systems with Leonardo

[Zerox100]

Synthesis problem

I synthesized vhdl codes for a big systems with leonardo. When i began ro post synthesize simulation some problem appeared. I traced errors and then find source of it. Controller and adder of my code was not synthesized correctly. I Synthesized it alone (without other block). It syntesized correct. I undestood when i synthesize all codes with a script, some part doesn't synthesize correctly even i thick "Preserve Hierarchy".
Does anybody can help me? Would you please write your idea?

 

[sandusty]

Synthesis problem

I haven't use Leonardo. But for a such a huge system. can you set "don't touch" (it will not re-synthesis your adder again but only take adder's boundary load and drive) on your adder and then apply boundary optimization on the higher hierarchy?