Problem with verilog testbench

verilog testbench

Hi.
I write a code for Full Adder simulation in verilog.I write a code for test it(Testbench).bbut when I run the code the following Error appears.(I am working with MaxPlusII)
Can you solve it?

module fa
(x,y,sum,carry);
input x;
input y;
output sum;
output carry;
//-----------------
wire x;
wire y;
reg sum;
reg carry;
//------------------
always @(x or y)
begin
carry=x & y;
sum=x ^ y;
end
endmodule


The following code is for test:

//‘timescale 10000 us / 10000 us
`include "fa.v"
module fa_tb();
reg x,y;
wire sum,carry;

//------
initial
begin
$monitor("%b,%b,%b,%b",x,y,sum,carry);
$dumpfile("fa.vcd");
x=0;
y=0;
#5 x=1;
#10 y=1;
#15 x=1;
#30 y=0;
end
endmodule

This Error Message Appears:
Errorroject has no output or bidirectional pins in top-level design file.

verilog testbench tutorial

u have problem in the instantiation of the design in the testbench, u have used a include file, may be u can use the below code:

//‘timescale 10000 us / 10000 us

module fa_tb();
reg x,y;
wire sum,carry;

fa fa(.x(x),.y,.sum(sum),.carry(carry));

//------
initial
begin
$monitor("%b,%b,%b,%b",x,y,sum,carry);
$dumpfile("fa.vcd");
x=0;
y=0;
#5 x=1;
#10 y=1;
#15 x=1;
#30 y=0;
end
endmodule

modelsim verilog testbench

I can not view the testbench results automatically after compile this program(in Maxplus).
fa.vcd file does not create after compiling.

why?

is max plus 2 support test bench

u have run the simulation before viewing the vcd file, compilation itself is not sufficent.

register file verilog test bench

I save/compile/simulate but VCD file dos not exist.
and the waveform editor dos not show the simulation waveform.
I examine it in Modelsim (not Maxplus) and there isnt any problem in it.
what is the problem?

how to define reg in testbench verilog

I dont think MaxPlus II can generate the VCD file. Its just a basic simulator that is provided by Altera. To generate and view VCD files you need to use ModelSim or VCS or SimVision. The same file will generate a VCD file when you run it on any of the above simulators.

verilog io testbench

i synthesize your code in xilinx ISE 9.1 and simulate by modelsim and i saw no ploblem but
i change your codes with remove codes below:

wire x;
wire y;
reg sum;
reg carry;


thats enough to define
input x;
input y;
output sum;
output carry;

i saw the same error in my project in the past
if you see this error sure you mistake in I/O definition in verilog module or testbench
or you define input or output in verilog module
and didnt define in testbench

at last i suggest you to use xilinx ISE 9.1 and modelsim. i did some complicated projects
using this software. thats very powerfull.

good lock

bi-directional testbench verilog

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After giving "$dumpfile("fa.vcd");", paste the below:

$dumpvars(1, fa_tb.fa);

hope, now it may capture the signal activities.