problem with translation from vhdl to verilog

Hello!

I want to implement a simple i2c controller to the Spartan2 FPGA provided with Xport2.0. I've got one source in vhdl (which i attatched to this post), but the problem is, that in order to make it compatible with Xport I have to instantiate the so called Primary source, which I have in Verilog.

So, I have downloaded the X-HDL 3 Translator and translated my source to verilog. Unfortunately, I cannot synthetize it under the Xilinx ISE 6.1i, which i use. I simply obtain many different errors.

Can you help me?

Thanks a lot in advance!!

Mateusz Wysocki

Converting from VHDL to Verilog (or vice-versa) is never a good idea. At least, not with an automated program.

First, you may never get the same formatting, so there will be a lot of adjustments to do to the output source, and the comments.

Next, there are some differences between VHDL and Verilog that can't be translated without knowing the context. It's the same analogy as translating english to or from another language. Sure, you can use Babelfish translator (for example, translating spanish -> english), and sure, all the words may be translated 'synthetically' correctly (word for word) to the other language, but reading it often make no sense. Why?, because the translater can't know the *context* (in other word, the *idea* that the writer had in mind). It's the same for VHDL->Verilog translation.

Look at the source in VHDL, and the one translated to Verilog. If the translater is descent, you'll have Verilog code that look like it match the VHDL code. But now, studdy the VHDL source, and *understand* the idea that the writer implemented, and then, look at the Verilog code. I'm sure that one of the first thing you'll tell yourself is 'gee, better start from scratch...'.

So, you have 2 choices, either convert to Verilog, only after understanding the concept of the i2c VHDL core, or use software that can compile mixed disign (VHDL mixed with Verilog).

Just my 2 cents...