ee_wmkab
Junior Member level 1
Xilinx ISE help
Dear ALL,
I am new to xilinx platform. When I creat the test bench waveform for simulation (using modelsim). It is hard for me to use the current user interface for setting the end of testbench in a very very long simulation (over 1000000 clock cycle). The method I am using is (1) drag the cusor to the the place I expected it to end or use the context menu "Set the end of testbench". However, It is time consuming when I want to creat a testbench file in over 10000000 clock cycle simulatio. Would you please advise some simple method to set the end of testbench in over 10000000 clock cycle simulation.
Million Thanks.
BR
Keith
Dear ALL,
I am new to xilinx platform. When I creat the test bench waveform for simulation (using modelsim). It is hard for me to use the current user interface for setting the end of testbench in a very very long simulation (over 1000000 clock cycle). The method I am using is (1) drag the cusor to the the place I expected it to end or use the context menu "Set the end of testbench". However, It is time consuming when I want to creat a testbench file in over 10000000 clock cycle simulatio. Would you please advise some simple method to set the end of testbench in over 10000000 clock cycle simulation.
Million Thanks.
BR
Keith