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Problem with setting the end of testbench in Xilinx ISE

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ee_wmkab

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Xilinx ISE help

Dear ALL,

I am new to xilinx platform. When I creat the test bench waveform for simulation (using modelsim). It is hard for me to use the current user interface for setting the end of testbench in a very very long simulation (over 1000000 clock cycle). The method I am using is (1) drag the cusor to the the place I expected it to end or use the context menu "Set the end of testbench". However, It is time consuming when I want to creat a testbench file in over 10000000 clock cycle simulatio. Would you please advise some simple method to set the end of testbench in over 10000000 clock cycle simulation.

Million Thanks.

BR
Keith
 

Xilinx ISE help

I'm not sure what you mean by "set" the end of the testbench.
I don't think I've ever seen the context menu item you mentioned.

Run for 10M clocks? I just say "run 100ms" or whatever time is sufficient.

Zoom in to view the end of the run? I say something like "WaveRestoreZoom 99.999ms 100ms"

I type those commands directly into the ModelSim command window, or I put them into a convenient "do" batch file and run them, "do mystuff.do"
 

Re: Xilinx ISE help

echo47 said:
I'm not sure what you mean by "set" the end of the testbench.
I don't think I've ever seen the context menu item you mentioned.

It's exist.
Check the waveform genertor.
:)

SphinX
 

Xilinx ISE help

What is "waveform generator"? I don't see it in ModelSim SE 5.8d or ISE 6.2.03i.
 

Xilinx ISE help

Salam,

I mean HDL Bencher window (Test Bench waveforms) :)
Drag the cursor to the end of your desire point in the waveform then click right and select "Set the end of testbench"

SphinX
 

Xilinx ISE help

Ah yes, now I recall that little ISE tool. Draw waveforms with the mouse, and it creates testbench code. I've never used it. It looks friendly, but too lightweight for my needs.
 

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