Problem with ripple of the LDO output

gdhp said:

hi all

i am designing a Low drop out regulator. the structure composes a band gap , a

error opamp, a pass pmos, a feed back resistance strings. The obtive of it is to

use the vref(1.2v) to generate the 1.5v output.

In my designing , THE error opamp using the folded cascode has the following character:
1: the DC Gain=100db, GB=70M
2: phase margin is 40

the load current is about from 100u to 5mA.

from the simulation results, i found the variation of 1.5v output is large.

so can anyone tell me how to compress the ripple of the output? is the pahase margin too small?

thanks!

Click to expand...

gdhp said:

the phase margin is the whole LDO's. The output is the 1.5v output!

Click to expand...

gdhp said:

to scottieman
i add the pulse current at the output. in the simulation , the output of 1.5v is variation.

to mitgrace
i don't use the current buffer. you mean use the current mirror at the output of opamp? can you explain it indetail?

Click to expand...

gdhp said:

hi all

i am designing a Low drop out regulator. the structure composes a band gap , a

error opamp, a pass pmos, a feed back resistance strings. The obtive of it is to

use the vref(1.2v) to generate the 1.5v output.

In my designing , THE error opamp using the folded cascode has the following character:
1: the DC Gain=100db, GB=70M
2: phase margin is 40

the load current is about from 100u to 5mA.

from the simulation results, i found the variation of 1.5v output is large.

so can anyone tell me how to compress the ripple of the output? is the pahase margin too small?

thanks!


You can check these item?
1.the variation of Bandgap
Make sure the variation come from bandgap or erroramp.
2."variation of output ",Do you mean Line regulation or load regulatoin?
3.DC gain is 10000 Gain*BW=70M BW=7K ?
The B.W is too poor.

Click to expand...

gdhp said:

hi all

i am designing a Low drop out regulator. the structure composes a band gap , a

error opamp, a pass pmos, a feed back resistance strings. The obtive of it is to

use the vref(1.2v) to generate the 1.5v output.

In my designing , THE error opamp using the folded cascode has the following character:
1: the DC Gain=100db, GB=70M
2: phase margin is 40

the load current is about from 100u to 5mA.

from the simulation results, i found the variation of 1.5v output is large.

so can anyone tell me how to compress the ripple of the output? is the pahase margin too small?

thanks!

Click to expand...

mitgrace said:

Dear gdhp :

Using current buffer , It is the between Opamp and Power MOS , It will enhace your phase margin in the totoal system . You can search the topic of LDO . This method is useful for LDO .

Click to expand...

rajath said:

mitgrace said:

Dear gdhp :

Using current buffer , It is the between Opamp and Power MOS , It will enhace your phase margin in the totoal system . You can search the topic of LDO . This method is useful for LDO .

Click to expand...

Can you please suggest any material which explains this concept further? By a current buffer, do you simply mean a source follower stage?

Click to expand...