nats_
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in the following code, the process doesn't seem to get beyond the elsif statement. any ideas why?
Code:
architecture div_arch of divider is
signal clks,resets,loads,divs: std_logic;
signal data_ins,data_outs :std_logic_vector(G_DIVIDER_SIZE-1 downto 0);
begin
data_ins<=DATA_IN;
clks <=CLK;
resets<=RESET;
loads<=LOAD;
divs<=DIV;
DATA_OUT<=data_outs;
main_sync : process (CLKs,RESETs,divs,loads)
begin
if RESETs = '1' then
DATA_OUTs <=(others => '0');
elsif CLKs'event and CLKs = '1' then
if loads='1' and divs='0' then
DATA_OUTs <= DATA_INs;
end if;
if loads='1' and divs='1' then
DATA_OUTs <='0' & DATA_INs(G_DIVIDER_SIZE-1 downto 1) ;
end if;
end if; -- clk if
end process;
end div_arch;