The IRQ output
remains low as long as the status bit causing the interrupt is present and the
corresponding interrupt-enable bit is set. The processor program normally
reads the C register to clear the IRQ pin. The RESET pin also clears pending
interrupts. When no interrupt conditions are present, the IRQ level is in the highimpedance
state.
Also, under what condition this interrupt is generated now?
ORG 0003H ;ISR for /INT0
LCALL INT0_ISR
RETI
ORG 0030H
MAIN: ;main line code
;some code...
;still more code...
;still some more code...
HERE: MOV PCON,#02H ;going to power down mode
SJMP HERE
INT0_ISR: ;ISR for my interrupt
;do stuff
;do more stuff
RET
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