Problem with PLL stability at higher frequency

[sonnyasu]

Hi, I 'm trying to make my pll work under certain input frequency range (from 2Mhz to 16Mhz with 4x 6x and 8x). I did stability analysis and plot the bode. It seems the phase margin is good enough (60 degrees), however, when I simulated at 16Mhz input with 4x multiplier, the system oscillates. At lower frequency everything is fine. Anyone knows why?

 

[saro_k_82]

pll 16mhz to 64mhz

The Bandwidth and all the loop dynamics change with the feedback division factor. If you want stable BW, then you need to adjust the Charge pump current such that ICP/N is always constant.

 

[sonnyasu]

pll 16mhz

well, the feedback factor is constant right? because the output frequency changes with the input step change. The feedback factor is determined by Fout/Fin so if Fin changes Fout changes accordingly if we have a fixed divider (this can be done easily). So my question is, with the fixed N, why do i see oscillation when changing the input frequency dramatically while the vco is still in range?

Basically, I have a system of dividing by 4 , 6, or 8. If i just choose to divide by 4 only, and changes the frequency from 4Mhz to 16Mhz with respect to the output frequency to be 16Mhz and 64Mhz. I 'm ok at 4Mhz input but oscillating at 16Mhz input. Anyone knows why? I checked all my equations and bode plots , phase margin is still larger than 45 degrees (matlab)... Confused..

 

[saro_k_82]

pll stability analysis

Then it must be the KVCO. This parameter usually changes a lot with the output frequency.

 

[sonnyasu]

Re: pll stability

my vco range covers all output ranges. My output range varies from 16Mhz to 64Mhz with 50% duty cycle. I simulated my vco over corners and temperatures and I got the range from 10Mhz to 101Mhz so I think the vco should be ok. The curve looks pretty linear to me. What else could cause the oscillation at high frequency?

 

[saro_k_82]

Re: pll stability

The VCO could work for a large range and it's gain could be linear as well., but this does not avoid the possibility of gain being vastly different for two different output frequencies. This is the only link I could suspect in this case.

 

[sonnyasu]

Re: pll stability

thanks for the reply.. So if the gain of vco varies by different output frequencies, how can I make it stable?

 

[saro_k_82]

Re: pll stability

That is exactly why it is difficult to have one loop covering a huge frequency range. You can have switchable resistors/capacitors in the loop filter to selectively control the loop parameters. Or you can have a lot of programmability in the charge pump current. Depending on your VCO architecture, you can include programmability in gain there as well.

 

[sonnyasu]

Re: pll stability

I think I know what you meant by adding switchable lpfs. I have those in my circuits to switch from 4x to 6x or 8x with different compensation scheme. The problem I m facing is at the same multiplier, e.x 4x, I swap the frequency from 4Mhz to 16Mhz from cold start and at 16Mhz the circuit will oscillate for the reason that I don't understand. At 4Mhz it's fine, no oscillation.