Problem with pipelined ADC when connecting to subconverter

[ronanchang]

Pipelined ADC

I am designing the pipelined ADC. And I have a problem. When I connect analog-to-digital subconverter (1.5 bit/stage) after SHA,the outputs of SHA are correct but the outputs of subconverters do'nt change. Is there something that I should take care?? The comparator is differential pair comparator. The analog-to-digital subconverter (1.5 bit/stage) is normal when I give differential sine-waves.

I am so sorry,my English is'nt good.
Thanks for your opinions.

 

[maxwellequ]

Re: Pipelined ADC

There must be someting wrong with your comparator or with the reference voltages that you are applying. You should check the internal nodes of the comparators to see what is the problem.

 

[ronanchang]

Re: Pipelined ADC

The power supply I use is 1.8V. So the reference voltages are 1.2V and 0.6V for positive and negative reference voltage respectively. Am I wrong for applying these values of voltages??

 

[terryssw]

Re: Pipelined ADC

What is your signal swing? why do you choose 1.2V and 0.6V as your reference? Is this reference for comparator input or full scale?

 

[mbright]

Re: Pipelined ADC

he must assume a 1.2v input swing.

so analog ground under 1.8v supply is 0.9v, the +1/4 ref is 0.9+0.3=1.2v and -1/4 ref 0.9-0,3=0.6v

my question is why u use a seperate SHA?
This shoud be combined with the subtractor-gain2stage, right?

myabe u design a parallel pipe. so u need a SHA to do time-interleaving?

what is ur comparator topology? better use a latch at the output, not the differteial pair only, that is just the pre-amp stage of a comparator.

acctualy we use dynamic latch only as comparator, its offset can be compenseated by the DEC. (u use 1.5bit/stage, so u have DEC)

 

[ronanchang]

Re: Pipelined ADC

In my pipelined ADC ,the first stage is SHA,after that is 1.5bit/stage.The 1.5bit/stage includes analog-to-digital subconverter and multiplying-DAC.
The multiplying-DAC will combine the subtractor-gain2stage.
The comparator I used is differential pair comparator including pre-amp and latch at the outputs. Yes,I will design the DEC circuits too.

 

[nxing]

Pipelined ADC

please post the schematic of your comparator .

 

[devrimaksin]

Pipelined ADC

If you can post a schematic
May be we can help

 

[terryssw]

Re: Pipelined ADC

I think he is using 2.4 Vpp differential swing, since he has +1.2V and -1.2V full scale differential reference voltage. Is it possible to turn on the transistor with such large swing in the comparator? You may have problems in the comparator pre-amp. 2.4Vpp differential swing is quite large in VDD = 1.2V. I think if he want 1.2 Vpp differential swing, which is quite resonable in such low voltage supply, then +1/4 ref = 0.9+0.6/4 = 1.05 and -1/4 ref = 0.9-0.6/4 = 0.75. Pls correct me if I am wrong.

 

[yeewong_su]

Pipelined ADC

can you post you CKT.maybe we can help you

 

[ronanchang]

Re: Pipelined ADC

The ciucuit I used for comparator is in the file.
S/H: Φ1 :smaple, Φ2:hold
comparator: Φ2:compare, Φ1:reset
But my comparator doesn't work in upper phases. It means that it can't compare in Φ2,but compares in Φ1.Actually it should not happen in Φ1.
Am I wrong for these phases in these circuits.
Or should I add some curcuit between S/H and comparator???
Thanks for everyone's opinion.

 

[terryssw]

Re: Pipelined ADC

I don't think this is some kind of comparator. Actually this is a traditional fold-around SC sample-and-hold circuit in the front-end of the pipelined ADC?