[SOLVED] Problem with output (output changes when it is not supposed to)

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;


entity q_multiplier is
	port ( a0 , clk, shift , ini : in std_logic ; 
			 mul: in std_logic_vector ( 4 downto 1); 
			 q0 : out std_logic ;
			 temp_out : out std_logic_vector (4 downto 1)
		   ); 
end q_multiplier ; 

architecture Behavioral of q_multiplier is
signal temp : std_logic_vector (4 downto 1); 
signal temp_ini : std_logic ; 
signal temp_shift : std_logic ; 

begin 
process (clk ,shift ,ini) 
begin 

temp_ini <= ini ; 
temp_shift <= shift ; 

	if (clk = '1' and rising_edge(clk)) then 
		
		if ( temp_ini = '1') then 
			temp <= mul; 
		end if ;
		
		if ( temp_shift = '1' ) then
			for i in 3 downto 1 loop 
				temp(4-i) <= temp(5- i); 
			end loop ;
			temp(4) <= a0; 
		end if ; 
		
		temp_out <= temp; 
		q0 <= temp(4);
end if ; 
		
end process ;
end Behavioral;
--

    wait for 100 ns;	
		a0 <= '1';
		shift <='0';
		ini <= '1' ;
  	   mul<= "1010"; 

		wait for 100 ns;	
		a0 <= '1';
		shift <='1';
		ini <= '0' ;
  	   mul<= "1010";
		
		wait for 100 ns;	
		a0 <= '1';
		shift <='0';
Here are 2 pictures of the waverform. Second one is just zoomed in 
[ATTACH=CONFIG]103037._xfImport[/ATTACH][ATTACH=CONFIG]103038._xfImport[/ATTACH]

LIBRARY ieee;
USE ieee.std_logic_1164.ALL;

 
ENTITY tb IS
END tb;
 
ARCHITECTURE behavior OF tb IS 
 
    -- Component Declaration for the Unit Under Test (UUT)
 
    COMPONENT q_multiplier
    PORT(
         a0 : IN  std_logic;
         clk : IN  std_logic;
         shift : IN  std_logic;
         ini : IN  std_logic;
         mul : IN  std_logic_vector(4 downto 1);
         q0 : OUT  std_logic;
         temp_out : OUT  std_logic_vector(4 downto 1)
        );
    END COMPONENT;
    

   --Inputs
   signal a0 : std_logic := '0';
   signal clk : std_logic := '0';
   signal shift : std_logic := '0';
   signal ini : std_logic := '0';
   signal mul : std_logic_vector(4 downto 1) := (others => '0');

 	--Outputs
   signal q0 : std_logic;
   signal temp_out : std_logic_vector(4 downto 1);

   -- Clock period definitions
   constant clk_period : time := 10 ns;
 
BEGIN
 
	-- Instantiate the Unit Under Test (UUT)
   uut: q_multiplier PORT MAP (
          a0 => a0,
          clk => clk,
          shift => shift,
          ini => ini,
          mul => mul,
          q0 => q0,
          temp_out => temp_out
        );

   -- Clock process definitions
   clk_process :process
   begin
		clk <= '0';
		wait for clk_period/2;
		clk <= '1';
		wait for clk_period/2;
   end process;
 

   -- Stimulus process
   stim_proc: process
   begin		
      -- hold reset state for 100 ns.
      wait for 100 ns;	
		a0 <= '1';
		shift <='0';
		ini <= '1' ;
  	   mul<= "1010"; 

		wait for 100 ns;	
		a0 <= '1';
		shift <='1';
		ini <= '0' ;
  	   mul<= "1010";
		
		wait for 100 ns;	
		a0 <= '1';
		shift <='0';
		ini <= '0' ;
  	   mul<= "1010";
		

      wait for clk_period*10;

      -- insert stimulus here 

      wait;
   end process;

END;