Hi,
During the Spectre netlist generation process, I have found out that the Assura QRC extractor includes the parasitic resistances of the MOS transistor bulk routing in the extraction view:
rg58 (vdda \5\:vdda) resistor r=24.5376 c=0
But, it skips connecting this parasitic resistor to the bulk of the transistor:
M10 (\3\:vout \5\:nclk \2\:vin vdda) p_lv_18_mm w=1.92e-06 l=2.4e-07 ad=2.224e-13 as=2.224e-13 pd=2.0u ps=2.0u m=(1)*(1)
From the line above, you can see that it circumvents the parasitic resistor and connects the bulk directly to the polarization net vdda (NOT \5\:vdda)
As a result, the simulation netlist generated from this extracted view is also incorrect.
I have tried two different technologies with two different design kits and both have the same issue. Two kits are:
1. Virtuoso Design Environment version IC6.1.3.500.13 with Cadence Extraction QRC - Parasitic Extractor - Version 8.1.4-p002.
2. Virtuoso Design Environment version IC6.1.5-64b.500.132 with Cadence Extraction QRC - Parasitic Extractor - Version 11.1.2-p106.
Is there any way to fix this problem? Can it be done by modifying the configuration script or updating the kit?
Thanks,
Stepan.