Hello every one,
I'm trying to design a pin placing between V6 FPGA and a DDR3 SDRAM with the part MT41J64M16xx-187E.
first problem is that this is not supported on MIG Tool when I select Virtex6, But It's available with Spartan6.
then I copy the specification I saw in Spartan6 MIG GUI and use in in V6 MIG GUI and use "create custom part" from GUI to create a new part.
Steps pass OK and and generation ends, but I see this problems.
1)there is no selectable "Burst Length" to select in Memory Option Dialog.
2) there is No A13 and A14 pin location in generated UCF file.
3) in a new MIG GUI when I select "Fixed pin out method" and reuse the created UCF file,
first step of pin assignments passes successfully but the BuffIO selection has errors :
"Insufficient pins for BUFIO:0...."
more info:
1) I'm using this banks:
bank 36-> Address/control
bank 26-> Data
bank 34->system clock.
2) Virtex6 FPGA is XC6vLX130T-ff1156 -1
3) Data width = 16.
4) Data Mask Enabled.
5) Other thing are default
6) I selected MT41J64M16xx-187E from SP605 schematics.
7) error :
8) Burst length problem:
9) MIG Version is 3.9