Problem with LVTTL/LVCMOS fanout chip

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EDA_hg81

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The follow is the 1-to-2 LVCMOS/LVTTL Fanout Buffer circuit.

The input clock is 30MHZ clock, which is working fine.

Clock1 is sent into FPGA, Clock3 and Clock4 are sent to two D Flip Flops(74HCT173DB,112).

But why the outputs from pin 5 and pin 8 of fanout chip are missing?
 

Have you probed all the chip pins to check all the inputs & power look OK? The circuit looks fine. Try removing whatever could be loading the clock outputs.

Keith.
 

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    EDA_hg81

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Hi hg81,
Is it OK for your design if Clk2 & 3 an extra 2.3nsec delay have to Clk1?
I mean do you wish it so? Others I would connect both ICs pin3 to Clk-In...
Check pls on both Vd pins(1/2&6) per Ohmmeter & on the IC pin direct that it has connection (zero Ohm) to VD`s 3.3V, than same for GND connections on bot ICs Pin 4&/!
Apropos; how high is your input clk pls?It must be minimum +2V peak & as zero down to maximum +1.3V if not at zero is...
Others said a pulse between 0...+2...+3V!
Its not clear me; you dont have some clks on all 4 outputs, or clk1 is in function?
K.
 

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    EDA_hg81

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Hi EDA_hg81,
From schematic what I understood id Clock1 is going to FPGA and also to fanout buffer IC.. Is it so? If yes then this may be the coz of your problem...
See FPGA holds signals if not used or in initial period.
Well what u can do is map some other clock to buffer input from FPGA instead of CLOCK1. What i mean is let the clock1 come through FPGA to the buffer. in this u can use this clock inside FPGA and u can map it to some global clock pin also.
 

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    EDA_hg81

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Thank you all for generous help.

Clock2 is fed to FPGA and Clock2 is fed to Flipflop.

I debugged the circuit and find out the value of those resistors are too high.

Best Regards.
 

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