problem with lvs in cadence layout using calibre

[ultrasonic.1991]

hi i'm trying to apply lvs test to the layout of my circuit that is a transimpedance amplifier which uses 4 spiral inductors . i encountered some problems . it gives 16 error which 4 of them is saying "incorrect instances" and point to the 4 spiral inductors . 3 of them is saying incorrect ports and point to the vdd , gnd and input port . another 9 errors say incorrect net and i dont know they are about what ! can someone help me with this errors i attached the file of my layout and my schematic

 

[rangermad]

It is usually better to post pics instead of files.

Try fixing your port problems first. Make sure your pins labels are correct.

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It is usually better to post pics instead of files.

Try fixing your port problems first. Make sure your pins labels are correct.

 

[tenso]

hi i'm trying to apply lvs test to the layout of my circuit that is a transimpedance amplifier which uses 4 spiral inductors . i encountered some problems . it gives 16 error which 4 of them is saying "incorrect instances" and point to the 4 spiral inductors . 3 of them is saying incorrect ports and point to the vdd , gnd and input port . another 9 errors say incorrect net and i dont know they are about what ! can someone help me with this errors i attached the file of my layout and my schematic

sounds like the problems I was having. In my case the label text was a different layer than the pins themselves. You might want to check that. After I corrected the issue calibre automatically reduced the number of parallel of devices.

 

[ultrasonic.1991]

i made some changes i checked what you said and now there is 1 port error which points to gnd 4 incorrect instance errors as it was before and 11 net errors. anything i do i cant solve the error about gnd port . i figured that when i put the lable layer to metal1-pin and the pin layer to metal- dg it has the least errors if i change both to metal1-pin it gives more port errors but however the error for gnd doesnt go away .