problem with lower FET in synchronous buck smps

I simulated (ltspice) and built this circuit (in actual fact I used Microchip fet drivers TC4432, TC4427, bigger caps - 2200uf, and 1/2 an SRS2525) and all was wonderful until built the circuit on a stripboard and tried it (duh).

The fets are 18mOhm @4.5V.

I used a micro to drive the PWM, SPWM inputs. The high side FET performed as expected, but the low side seems to drop -300mv and the diode -500mv instead of the expected 10mv/300mv resp.(I purposely exaggerated the dead times so the diode would have time to conduct).

The gate to the fet is approx 5V and I measured it and the drop on the FET itself, so it isn't a case of bad connections/track resistance.

I replaced the FET (same result) and tested the removed FET in both directions and it dropped some 5-6 mv @400ma (peak current by the simulation) as expected.

I want this circuit to be a solar charger, so the input will be 18V @5amps, output 12V@7amps more or less - but I wanted to test it at smaller (less damaging) voltages.

Any ideas?
thanks

How do you exactly measure the transistor voltage? A small probe compensation error will ruin any accurate voltage mesurement.

I'm using an old 60MHz Tektronics analogue scope; however, the probes are compensated correctly (albeit to a very slow 10Khz calibration signal). I can read all the other waveforms in particular the high-side measurement (same signal) which shows no such voltage drop. As well the difference between 300mv and 10 is quiet huge, even for an ancient scope!

thanks
mike

Could this simply be that the ground is both reference
and current-loop-component for the low side, but not
the high side? That is, ohmic ground rise might account
for much of the anomaly, especially when using inferior
PCB layout.

First of all, I should have mentioned that I a retired software weenie, who only knows enough about hardware to hurt myself!

That said I was (am) pretty proud of the layout even if it is on stripboard, as it is very clean and the intention is to add #14 copper wire (didn't figure it was neccessary with a few hundred mA) to the ground and the track joining the two FETS, the gate lines are short ...

Regardless, the point I can't figure out is that I measure the drop on the FET, i.e. between the source and the drain. To clarify and add to my response to FvM, I have the scope triggered on a pwm signal. I look at the trace for the source (gnd) with the probe connected to the FET's pin and it is "exactly" gnd with some noise at the transitions, then I connect the probe to the FET's drain pin and observe the 300mv difference. Even if the layout was lacking I would see the ground lift (fall?) on the source pin.

I was inclined to think along FvM's lines, i.e. some measurement error though the efficiency is only around 80% and I expected much better from a synchronous design.
I can't imagine why I should measure (see) expected behaviour for the high side FET and not the low side as it is the same signal that switches from 10V to -300mv.

It's as if the FET has higher (much) impedance in the reverse direction as I have already tested it is the same dc on resistance.

Much thanks for the ideas, it will turn out to be something dumb (I hope), at this point I don't really know how to test, tweak the board to figure it out

mike

I agree that 300 mV is relative large related to 10V switch swing and should be clearly recognizable. But I don't see other explanations than measurement error if transistor is actually switched on by 5V Vgs.

To measure switched on-state voltages at a much lower level, I have connected a schottky clamp between Vds and probe, e.g. 1k and a fast diode. Because the AC swing ist mostly removed, probe and oscilloscope amplifier compensation errors don't disturb the measurement.

"The more I know the more I know I don't know"

Still perplexed, but convinced that the problem is measurement error and not some layout or some strange FET behaviour I didn't understand.

Changing the load current did not seem to affect the measured drop across the fet, but did across the diode (as I would have expected).
I increased the load to 800ma and the FET remained cool, which it would not have done dropping even 100mV (1/2W) and certainly not >200mV.

When I increased the source voltage to 20 V and the output voltage 10V I saw underswing in the gate voltage (now 10Vpp). Curiously I saw no overswing in either the gate, nor in the drain voltage (I set the scale at 200mv/div and used the offset to view the 10V/20V traces.

It's time to up the ante and put a few amps through it.

Thanks for all the help

mike

Your schematic shows M2 in conventional orientation.

However in a synchronous buck converter, when it turns on, it conducts current UPWARD from ground, into the coil L1.

This means that M2 should be reversed, source for drain (if your real circuit matches the schematic).

This means that M2 should be reversed, source for drain (if your real circuit matches the schematic).

Click to expand...

That's, excuse me, simply BS. MOSFETs can well conduct in reverse direction, I presume you already utilized the capability, apparently without noticing it. "Reversing" M2 will make the MOSFET diode short the converter output.

FvM said:

That's, excuse me, simply BS. MOSFETs can well conduct in reverse direction, I presume you already utilized the capability, apparently without noticing it. "Reversing" M2 will make the MOSFET diode short the converter output.

Click to expand...

I guess you got me. I must plead 'simulator goggles'. The mosfet model lacks a body diode, and I find that the mosfet needs to be upside-down if current is to flow properly when simulating a synchronous buck converter.

Since years back I was aware JFET's had interchangeable drain and source. And I remember that made them different from mosfets, for a while at least.

I believe there was also a time mosfets did not have body diodes.

Anyway it makes me wonder about the action of the low-side mosfet in the schematic. Namely as to:
* Which pin the gate should be referenced to?
and
* What voltage is applied to the gate, with reference to that pin?
and
* Whether the mosfet is turned on immediately as the high side mosfet turns off?

Also:
* Whether the mosfet is really turning on fully (which will produce the desired small voltage drop),
or
* Whether the body diode is carrying the burden as a freewheeling diode (which could produce a greater voltage drop)?

The basic MOSFET transistors in digital logic ICs are in fact symmetrical, you can interchange source and drain electrode without changing the behavior, quite similar to symmetrical JFET. Circuit like transfer gates are utilizing the symmetrical behaviour.

Power MOSFET have a different geometry and are asymmetrical in two regards:
- source to substrate short which connects the body diode parallel to the transistor
- asymmetrical gate and channel geometry with high voltage strength for the drain side

In principle you would refer the gate voltage always to the terminal acting as source, e.g. the most negative terminal of a NMOS transistor. But because the reverse voltage of power MOSFET is limited to 0.7 V, you don't need to care about the difference in most cases.

Transistor output characteristics in reverse operation are rarely shown in datasheets. Due to the small voltage range, you can extrapolate the Vds 0..0.5 V ohmic range to the negative side without introducing large errors.

Optimal gate timing of a transistor in reverse operation ... depends. In a converter with bidirectional current flow the transistors can work both in forward and reverse operation. The control signal timing is mostly chosen to be suitable for both operation modes.

Body diode current involves these aspects:
- no "on" switching losses, short initial diode current flow can be beneficial
- high forward voltage, transistor should be on for most of the time
- high "off" switching losses with slow body diodes, avoid temporary diode current during transistor turn-off

In addition, MOSFET with slow diodes have a rather low diode commutation dV/dt maximum rating, exceeding it will involve excessive current peaks and possibly transistor failure.

JVM,

Continuing somewhat off-topic (but not really), I never really thought about the gate reference "switching" in reverse conduction, but I will add the observation that this effect will considerably slow down the transition times as this adds negative feedback to the gate(pin)-source(pin) signal - by a factor of 8 for the NTD4963N (if one can trust the manufacture's spice model!)

I also understood that the body diodes were slow and because I wanted to play with dead time I added the SRS2525 in my circuit to prevent the body diode from turning on, but this is the first time I have heard of a problem with dV/dt

I just checked the data sheet and it appears that the Trr is quite fast, though I guess the rub is the 100A/us dIS/dt test conditions, but I also looked at Microchip's FETs and they specify the Trr at 300V/us.
https://www.onsemi.com/pub_link/Collateral/NTD4963N-D.PDF
https://ww1.microchip.com/downloads/en/DeviceDoc/20002329B.pdf

Is there any way to infer maximum acceptable dIS/dt from the datasheet?

These are within an order of magnitude of the turn on times of the upper FET, but in the simulation there are massive, very fast spikes is that a simulation artifact or is it likely in practice?

thanks
mike

Diode commutation dV/dt is particularly a problem for high voltage MOSFET Vds > 600V. Specifications can be found at least in Infineon datasheets.

I went looking at some data sheets for high voltage FETs, found the spec and then noticed it is on the NTD4963N spec but not the MCP87018. The NTD4963N specified a "Drain to Source dV/dt" spec of 6V/ns which seems pretty fast (for low voltage stuff). I don't understand the 100A/us dIS/dt test conditions, but otherwise these two FETs seem to be faster than most fast recovery diodes.

Thanks for the insights FvM

mike

Save yourself some hassles and get a driver chip. ie IR2184S. It will handle the high and low side drive and you only need to use 1 micro pin to drive. It's a half bridge driver chip , perfect for this application. Dead time is fixed in this chip , but there are others which
have a settable (via resistor) dead time.
Neddie

neddle,

Thanks for the comment, I wanted to experiment with dead times to see how good a software hunt for min dead time would work. The IR2184S has rather long dead times (500ns) and I thought I really didn't want the lower diode to turn on.

As it now turns out, the particular PIC I had chosen is particularly power hungry (120ma), plus from the discussion above, unless I am missing something the diodes on these FETs are faster than fast recovery diodes.

Regardless the board is built and apart from my measurement issues appears to work, I'm just playing with the software now.

As a side note I need two modules, so on the second I will try a driver chip - the MCP14628 is designed specifically for buck converters and has adaptive dead time.

mike

Just to confirm what we already knew, I put 50 watts (output of 10V 5amps) and all remained cool.
I had trouble measuring the actual efficiency - I measured 99-102% - with about 3% known calibration errors, plus there is a fair amount of ripple (which will not be an issue hooked up to a battery) and I was only measuring averages of voltage and current instead of power ...
Regardless, its efficiency would seem to be in the high 90's so i am quite happy.

Thanks again for the comments
mike