[SOLVED] Problem with 'logical anding' in Verilog !!

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osm3000

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Hi everyone,

I've this annoying problem in my Verilog code.

This my code

HTML: 
always @(posedge REF_CLK or negedge all_reset)
  begin
    if (~all_reset)
      TSM_R_B_N <= 1'b0;
    else if (clr_r_b_n)
      TSM_R_B_N <= ( (1'b0) && LUNSTATUS6 );
    else if (set_r_b_n)
      TSM_R_B_N <= ( (1'b1) && LUNSTATUS6 );
  end

What I want is to simply OR 'LUNSTATUS6 ' signal with another value - depending on a flag - and assign this to 'TSM_R_B_N '.

In the waveform however, when 'LUNSTATUS6' changes to 0, 'TSM_R_B_N' doesn't make any change.



Can anyone give me a help?
 
Last edited:

Could be a race condition. How are the other signals being assigned? with non-blocking assignment? You can run vsim -nowlfcollapse to recode the exact order that variables change within a time-step. See the section on "Expanded Time in the Wave Window" in the User Manual.
 

Well, the sensitivity list is as you made a flip-flop, so the TSM_.. will change only when ref_clk will rise.
And 1'b0 && ... Will always give 0, 0 and what you want equal 0.
The or is made with |.
 

Thanks dave_59 and rca for your replies.

I actually discovered that the problem is much simpler - and honestly I feel really stupid about it -.

The flags 'clr_r_b_n' and 'set_r_b_n' aren't working properly. I was actually looking at the wrong waves for these flags.

As soon as I fixed this, the problem became an issue with the logic itself.

This is the code after fixing

HTML: 
always @(posedge REF_CLK or negedge all_reset)
  //always @(*)
  begin
    if (~all_reset)
      TSM_R_B_N <= 1'b0;
    else if (clr_r_b_n || ~LUNSTATUS6)
      TSM_R_B_N <= 1'b0;
    else if (set_r_b_n || LUNSTATUS6)
      TSM_R_B_N <= 1'b1;
  end

This will make the right behavior.

- - - Updated - - -


Thank you for this information. Also this it turns out that this is not the case here, yet I made use for this in other parts of my code. Thanks a lot.
 

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