Problem with leakage in power MOS for LDO regulator

[mitgrace]

A power MOS for LDO

Dear All :

I have design the LDO regulator , and our PMOS is external componet , But now the LDO is wrong behavior , Becasue the PMOS gate induce some leakage , so that the OP amp can't work well . Does anyone know how to solve this problem , Or anybody know which POwer MOS is good ?

PS , I use SI2301 .

Thanks

 

[sunking]

Re: A power MOS for LDO

try to add the current of OP last stage :wink:

 

[mitgrace]

A power MOS for LDO

Excuse me , You mean add current buffer , How do design this , Do you have paper ,or schematic , Thanks

 

[rauol]

Re: A power MOS for LDO

8) i think it is due to noise, just add one resistor of around 100K from gate to source and check.

 

[andy2000a]

Re: A power MOS for LDO

sorry .. how large leakage current about your powerMos ??

as I know power Mosfet Ids =6A Cgs=1000p leakage = 0.1ua (Vds=0
Vgs =20v) or SI2031 have large leakage current ..

 

[mitgrace]

A power MOS for LDO

Dear All :
I Summary my measure result , I don't add the current buffer bwtween the OP and Si2301 , Now I mean the Open loop of OP , The Behavior ir right , But When I coonet to the close loop , the Behavior is wrong , the V+ is 1.8v , V- is 1.2 form Bandgap , the the the out of OP is 0.777v , So that I measure the stand alone the PMOS , I add a big resistor(7M) in the Gate , and I force the volatge(2.2) to Resistor , then measure the Gate volatge is 0.77v, It seem the Gate have some leakage cuurent , That I measure it , My questions is How do force my LDO to correct DC mode , Thanks

 

[mitgrace]

Re: A power MOS for LDO

PS . Our system is 3.3v convert 1.8v , We use 3.3 MOS to design this LDO regulator , Thanks

 

[sunking]

Re: A power MOS for LDO

There are flowing you should measured:
1. you can measure the leakage current by an amperemeter, how much?
2. measure the output by ac, maybe the close loop is osc.
3. test the output Pmos vth