Problem with layout during parasitic extractio, please help!

[jacksimonbirch]

causes multiple stamped connections

Hi,

My layout pass DRC check, but when I try to do parasitic extraction, it give me errors.
here is the error message:
2 Figure Having Multiple Stamped Connections.
6 Figure Causing Multiple Stamped Connections.

The M1_NWELL and NWELL are the cause I guess, but I have no idea how to fix this problem. I have tried many way only to reduce the errors but couldn't get rid of it.

Please help!
Also, please explain what the error message above means.

Thanks

 

[selvaraja]

extract causes multiple stamped connections

Do check your device difinision in your extraction file.

 

[maxwellequ]

diva figure having no stamped connections.

Those errors appear when you have the substrate or an n-well connected to 2 or more different nodes.

Regards

 

[Question]

cadence, layout, pimp

If yo use Cadence and diva rules, add a 'skip_soft-connect-checks' switch when do extraction.

 

[Hughes]

cadence diva switch extract parasitics

If yo use Cadence and diva rules, add a 'skip_soft-connect-checks' switch when do extraction.

Switch names are rule deck specific. Your rule deck has suck a switch, but others may or may not have such a switch. If there is a switch, its name may be different.

 

[jacksimonbirch]

figure causing multiple stamped connections.

I found out yesterday that the problem cause by having different net connect to the subtrate just like "maxwellequ" said. I also found that my CAP causing that error. When I took the CAP out the error went away.

So, does anyone knows how to connect the "nmoscap" to the circuit without getting that error?
the nmoscap has 3 connectors (1 connect to Vss, and the other 2 connect to the transistors).

I heard that I have to cover the CAP with some layout such as Pimp/Nwell to make it work.

If anyone knows how, please show me.

Thanks

 

[Hughes]

If you use normal enhancement nmos (nmos outside nwell) as cap, the S, D and B terminals should be tied to VSS. Only the G terminal can be connected to other node. If you want a mos cap not connected to VSS, please use mosfet in nwell -- either nmos in nwell or pmos in nwell. On the latter case, the mosfet should be properly biased.

 

[Question]

if you use nmos as a cap. u should connect D, B, S to low, and connect G to H.

 

[Teddy]

Re: Problem with layout during parasitic extractio, please h

I would just add - run LVS before you run parasitic extraction => extract no parasitics just active devices. It helps.