Hi,
Again I dont know why it is happening. BUT,
by design, you should not have any flip flops, undefined at the start up, if they are cticial for the funtionality.
As if a register is a wirte_enable to a fifo, then this register MUST not be coded, without having a defined reset going on to it.
Its not one of the best practices to leave these registers at the mercy of xilinx or any other tool.
Think, if you dont put a reset to the 'critical' registers in a design, then at power up they may take up any value, and kill your funcionality. Well this is what happens in ASIC, for FPGA I am not sure, may be xilinx put random init values to the registers not defined at power up or having no reset at all. And that is why you are having different init values for different registers in your design.
A better design will always be well thought of and will NOT have any critical register uninitialized.
Kr,
Avi