Problem with including variables in VHDL for state machines

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Re: Variables in VHDL

It's about fixed point not floating point.
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LOL.. The term 'fp' has been embedded into me as floating point.. So when i read any sentence with a word 'point' in it, i will still register as floating point.

Seeing that i have only started learning VHDL 10 months ago, i don't really understand the standards involve. (from the link you have shown me)

I will make do with standard_logic_vector then. Wanted to know if there is any efficient way to do the conversion fast.
 

Re: Variables in VHDL

As I said, all operations most likely required in your application as defining a fractional number representation for integer quantities, scaling of multiply results, saturation logic to avoid numeric overflow can be handled with standard arithmetic packages as well. I just wanted to mention the existence of the fixed point IEEE library. For a small project, you possibly go faster when ignoring the option.

Synthesized results should be similar, provided, both variants are applied meaningful respectively.
 

Re: Variables in VHDL

Thanks. Managed to resolve it.

Didn't realise that the below are not the same when "a" is a std_logic_vector.

a <= a * 5; -- this gives error

is not equivalent to

a <= a * "101";
 

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