Problem with including variables in VHDL for state machines

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ombadei

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Hi,

I'm using ISE10.1 to code my VHDL and program the resultant bit file in a spartan kitset.

I have many state machines declared in my application. When i include variable integers in my loop control, the result that i obtain in my state machine has unpredictable results.

Any rationale reason to it?


THanks
 

variables vhdl

In VHDL, variables are assigned the values immediately unlike signals. This means inferring latches that are not preferable and in some cases with unpredictable results. So, try to replace your variables with signals.
 
variables in vhdl

Thanks..

What about the behaviour of "signal integer" versus "signal std_logic"?
 

vhdl variebles

Integer involves a higher level of abstration. In state machine design, you typically use specific enumerations to improve the readability. They can be understood as an alias of an integer range.

Integers without a range can be a problem if the intended bit length can't be recognized by the design compiler.
 

variable and signal difference vhdl

Do correct me if i am wrong.

Can i say that, if i specify a signal integer with a range , i would expect it to behave exactly like a signal std_logic vector?

Or would i consider the design compiler's method of generating?
 

declare variable with range in vhdl

I believe that range-restricted integer signal is the same as bit vector .. I'm not sure if it's going to be translated to std_logic or not. Still, if you declare integer range 0 to 31 for example, it will be implemented as 5 bits. (00000 -> 11111). This also implies that all the operations are going to be unsigned as you declare the range to be only NATURAL.
 

vhdl for loop control variable

Thanks.. It has been most insightful..

Not wanting to start a new thread..Consider the below 2 code segments.. Is there a difference in compiling or implementing the design?

Code: 
process(clkin)
begin
clkout <=clkin;
end process;

Code: 
Architecture of blah behaviourial
begin
clkout <= clkin;
 

unsigned variables in if condition in vhdl

Not yet. It may be the case, when additional code involving clkout is added.
 

unsigned variables in if condition in vhdl


Do you want the (clkout) to be an identical copy of (clkin) ?
 

how to give range with integer in vhdl

The two codes are not the same. The difference is seen after the synthesis. The first code will require some circuits to be done (A flip flop with CLK and Input connected to CLKin)
The second code will be implemented simply by connecting together clkout and clkin.
 

signals and variables in vhdl

The first code will require some circuits to be done (A flip flop with CLK and Input connected to CLKin).
Click to expand...
Look sharp! Do you see an rising_edge(clk_in) condition that instantiates a flip-flop?
 

vhdl condition variable


How do you imagine the tool will implement it ?
 

vhdl variable flip flop

In my opinion, both statements will give identical results .. clkout <= clkin is itself considered a combinational process. The only difference is that you can't add more circuitry to the statement, while with the process statement you can do more.
 

sensitivity list definition process

omara007 said:
In my opinion, both statements will give identical results .. clkout <= clkin is itself considered a combinational process. The only difference is that you can't add more circuitry to the statement, while with the process statement you can do more.
Click to expand...

Sorry omara007,
I dont see thinks like you.
The code are differents. In the first code the process run only with a clkin even.
So clkou<=clkin at rise or falling edge or clkin.
For the second clkou=clkin, it's a wire.

Simulate them and you'll see the result are differents.
 

vhdl variables multiple assignment

Do you want the (clkout) to be an identical copy of (clkin) ?
Click to expand...

Just trying to understand the semantics of the circuitry involve.


So, does that mean the one with the process statement will not infer a flip flop?

What was taught in school mentioned about sensitivity list signals in the process(sensitivity signals) statement. And i kinda conclude that if a signal change were to happen in the parenthesis, an event will happen. I think this is what AdvaRes was referring to.
 

vhdl variable sensitivity list

The code are differents. In the first code the process run only with a clkin event.
So clkout<=clkin at rise or falling edge or clkin.
For the second clkout=clkin, it's a wire.

Simulate them and you'll see the result are differents.
Click to expand...
You may want to think a moment about the possible different behaviour. You'll realize, that there is none - in this special case even in simulation, because no other signals are involved. Clkout is immediately following any change of clckout in both in both cases. It's obvious in the concurrent code, the wire case, but you get the same behaviour in the sequential code, the process, because of the sensitivity list.

If using VHDL in logic device synthesis, you would also know, that a sensitivity list has a meaning only in simulation but not in synthesis. Thus an assignment as clkout <= clkin, appearing once in a process, without an additional condition in effect always infers a wire, independant of a sensitivity list. Although this behaviour isn't specified in the VHDL standard, it results clearly from the way, the logic can be implemented. A flip-flop will be never implemented from a similar code without an edge sensitive condition. Your invited to try with a free vendor tool, e.g. A.ltera Q.uartus.
 

state machine variable vhdl


Hi AdvaRes

Did you notice that this process [process(clk)] is considered combinational as long as you didn't specify an edge event inside ? .. in this case, the combinational process will yield exactly the same result as the combinational direct assignment statement. If you saw different results in the simulation, please post the snapshots here in the thread.
 

variables en vhdl

Yes, exactly.

However, there are two possible differences with a more complex process code. Thus I said, there's not yet a difference.

1. If clkin would be missing in the sensitivity list, changes of cklin can be ignored in simulation (but not in synthesis)
2. In a process, you can have multiple assignment to a signal, e.g. clkout. While this would be flagged out as a mutiple-source error in combinational code, it's legal in sequential code. Simply, the last assignment wins.
 

why use vhdl variables


Hi members,
Theoritically it's true but I remember that this is not permitted by the tool when then CLOCK is in the sensitivity list like that.
 

how to declare unsigned integer variable in vhdl

AdvaRes said:
Hi members,
Theoritically it's true but I remember that this is not permitted by the tool when then CLOCK is in the sensitivity list like that.
Click to expand...

If you specified an edge event to any signal, the tool deals with it as a clock .. if not, the tool deals with it as a normal signal. So, the tool will not complain if you specified any clock in the sensitivity list without specifying any edge even inside the process body.
 

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