Problem with Hyperterminal to connect FPGA

Hello guys, I have a question.
I use Hyperterminal software to send a file to FPGA. I implement a UART Rx in FPGA and loopback it to UART Tx and again I want to return back same character that I send to FPGA in Hyperterminal.
but I have some problems. It's work for about 8000 character for 4800 bps baud rate and next it has about 20-50 false character and next it's work again! after about 8000 character it's a false character and it continue ... In FPGA I can't make an exact clk and it has about 1 Hertz deviation. I use Win 7 and I use portable Hyperterminal. also I use ISE 14.3 and my device is SP6 LX45. what do you think? It's related to my VHDL code or it's related to Clock? What I do? I want to send a file about 200 KB and I want there aren't any false character in receive side. Can you help me?
Thanks for your comments ...

Hi,

In FPGA I can't make an exact clk

Click to expand...

How this? With RS232 you need a frequency accuracy of +/- some percent. In FPGA you should be able to generate frequencies with some hundred ppm accuracy easily.

1Hz deviation with a desired frequency of 10Hz gives 10%. 1Hz deviation with 1MHz gives 1ppm.

To your problem:
Do you use oversampling on fpga uart input and adjusting to incoming edges - at least on start bit edge?
What is your protocol setting? 8N1?
4800 bps is kind of slow...

Klaus

Hi,
try standard UART module that comes with XPS. it is standard module and probably help you to find your problem.

The sampling clock on your FPGA should be at least 16x your baud rate.

r.b.

Yes I use 16x clock to track the edge. I use 8 bit data + stop & start bit without parity and flow control. When I use 4800 bps baud rate, if I make a clock 4801 Hz after 4800 clock we have an extra clock and data was corrupted. Am I right? If it's correct and you can't make an exact clock what we do?
And I don't know about XPS, can Miralipoor explain it?

Why are you making a 4.8 kHz clock at all? What use do you have for it? The 16x sampling clock is all you need to capture the data.

Hi,

did you read UART or even better RS232 specification regarding baud rate tolerance?

i don´t know the exact value but it shoud give no transmit error even when working with 4825Hz.

You have to adjust sample timing with falling start bit edge. for every byte. This is, what i remenber, but better read through the documents.


Klaus

I must use 4800 Hz clock to send data from FPGA to Hyperterminal. I can't change the sampling time because it's related to Hyperterminal. You say when you use 4825 Hz clock, it's work. but why? it make an extra clock after 4800/25 = 192 clock and it make an extra bit. Am I right?

As Klaus said you synchronize to the falling start bit edge. So you only need to be accurate for 10 clock cycles.

I know it. It's for sending data from Hyperterminal to FPGA that I use 16x clock and detect the edge, but in transmit data from FPGA to hyperterminal we send data at 4800 clock. now if our clock was 4801 Hz what we dooooo?

Hi,

Dont´worry about the PC side, be sure, the receiver at the pc makes it right.
It also adjusts to the falling edge of the start bit.

Don´t worry about 4800 or 4801 or 4825. All will work without errors caused by baudrate mismatch. .

read specifications.

Klaus