[SOLVED] problem with gate-level simulation

[yushionly]

tools:design_vision and nclaunch
in my .v file i write a multuiplier(8*8), when i do functional analysis,the result is correct, but when i do gate-level analysis,the output result is uncorrect,what is the matter?
0x06 * 0x04 = 0x18 (functional)
0x06 * 0x04 = 0xX8 (gate_level)
and after gate-level analysis,i got a mult-8-8-0.db file

Thanks a lot!!

 

[chipmonkey]

can you try initializing all registers before you start the simulation run. Basically make sure all flip-flops have some valid value (0 or 1 NOT x) at the beginning of simulation.

The x can also appear if you have multiple drivers for the same signal.

 

[yushionly]

thanks for your reply,but i have initialized the registers,and its just a multiplier,it does not have multiple drivers

can you try initializing all registers before you start the simulation run. Basically make sure all flip-flops have some valid value (0 or 1 NOT x) at the beginning of simulation.

The x can also appear if you have multiple drivers for the same signal.

 

[chipmonkey]

thanks for your reply,but i have initialized the registers,and its just a multiplier,it does not have multiple drivers

Is it timing simulation? any violations?

 

[yushionly]

Is it timing simulation? any violations?

yes ,it is timing simulation. and functional analysis is right ,but gate-level simulation has problem

 

[chipmonkey]

If the simulation is proper on Gate level without SDF, then it could be a setup/hold violation that is causing the issue in timing simulation.

 

[yx.yang]

yes ,it is timing simulation. and functional analysis is right ,but gate-level simulation has problem

So it's simple now. You just need make your clock run slowly. Such as 1MHZ. HaHa.

 

[yushionly]

If the simulation is proper on Gate level without SDF, then it could be a setup/hold violation that is causing the issue in timing simulation.

i have solved the problem ,thanks a lot
when i use sdf file, i get correct result!