Problem with finite state mashine (ISE6.3 + Spartan3)

[Delsian]

My design sometimes locked in real chip but works well in simulator. I found that FSM switched to undefined state time by time. When I changed syntesze option "FSM encoding algorithm" from "Auto" to "Compact"- all starts to work fine, but compiling time increased.
In "case" exists "when other => nextState <= stIdle;" but not helped to avoid undefined state in "Onehot" encoding.
There is problem in chip, in design or in my head?

Added after 1 hours 31 minutes:

I checks all encodings - locks only "One Hot", all other algorithms works fine. Maybe, problem in ISE?

 

[it_boy]

You cab try post place and route simulation to find out what the problem is

 

[Delsian]

Question closed - it's my mistake, two input signals changed simultaneously.
Now all works correct even in OneHot encoding.