how to make a phase lock
Do you really mean hertz? That is pretty low frequency.
What modulation are you using for the 100 Hz data?
If you are using something like BPSK, sure a 110 Hz loop bandwidth will be ok. But you have to fool around with the poles and zeroes of the loop filter to make it stable. You will have a relatively large time delay component, since you only get 8 samples of carrier sine wave in which to determine what phase the carrier is at for each data period. You have a time delay of 1/800 Hz for the first sample, and then the next phase sample is delayed another 1/800 Hz in time. Such a time delay will affect how the loop filter responds. In control theory books this is called "transportation lag", and to a first order it looks like extra phase shift in the control loop. That extra phase shift tends to make the loop more unstable, so you need to do some extra stuff to insure phase margin and gain margin in the loop.
If simulink can model the complex time delay, it is like multiplying the open loop response by e^-τS. In frequency domain terms, the phase shift at a given control loop frequency is Θ = -ωτ, where your ω = 2 Π 110 (your open loop bandwidth), and τ = 1/800, or in other words, -49.5 extra degrees of phase shift in the open loop transfer function at its 0 dB crossing!