Problem with encoder counting code in VHDL

[btminzon]

Hi everyone. I´m implementing a encoder counting (two square waves, dephased 90º each other, bidirectional) in VHDL, but Quartus II is generating a error message "Error (10820): Netlist error at Altera_Minitech_VHDL.vhd(52): can't infer register for Counter[] because its behavior depends on the edges of multiple distinct clocks". Ok, i know, but, how can i do this in VHDL? my code is below. In the code there isn´t syntax error. If any, copy-paste problem. Thanks a lot

entity Altera_VHDL is
port (
Clock: in std_logic;
Channel_A, Channel_B,Channel_Z: in std_logic;
Busca_Referencia: in std_logic;
Enable: in std_logic;
Data: out std_logic_vector(6 downto 0);
);
end Altera_Minitech_VHDL;

architecture Altera_VHDL_arch of Altera_VHDL is
component D_FF
port (
D: in std_logic;
Clock: in std_logic;
Q: out std_logic
);
end component;

signal reset: std_logic := '0';
signal R35: std_logic := '0';
signal R34: std_logic := '0';
signal Counter: std_logic_vector(6 downto 0) := "0000000";

begin

R35_DFF: D_FF port map (not Channel_Z,Clock,R35);
R34_DFF: D_FF port map (R35,Clock,R34);

reset_counterrocess(Channel_Z,Busca_Referencia,R34,R35)
begin
if (Channel_Z = '0' and Busca_Referencia = '0' and R34 = '0' and R35 = '1') then
reset <= '1';
else
reset <= '0';
end if;
end process;

contagem_pulsosrocess(Enable,Clock,Channel_A,Channel_B,reset)
begin
if (Enable = '0') then
Counter <= (others => 'Z'); --Tri-State
elsif (reset = '1') then
Counter <= (others => '0');
elsif (Clock'event and Clock = '1') then
if(Channel_A'event and Channel_A = '1') then
if(Channel_B = '0') then
Counter <= Counter + 1;
else
Counter <= Counter - 1;
end if;
elsif(Channel_B'event and Channel_B = '0') then
if(Channel_A = '0') then
Counter <= Counter - 1;
else
Counter <= Counter + 1;
end if;
end if;
end if;
end process;

Data <= Counter;


end Altera_VHDL_arch;

 

[jep]

Help in VHDL

elsif (Clock'event and Clock = '1') then
if(Channel_A'event and Channel_A = '1') then

Q II can't refer any register from these two lines and i think you can not expect Q II understand it while no register can meet your requirement

 

[mpatel]

Re: Help in VHDL

Hi btminzon,

Jep is correct, you can not have another signal edge trigger event after clock_edge_trigger. It will always gives error. and it is also NOT NECESSARY!

Use only level trigger.
eg. if rising_edge(clock)then
if channel_A='1'then

this will work.