entity test is
Port ( en : in std_logic;
a : inout integer;
c : out integer);
end test;
architecture Behavioral of test is
begin
process(en)
begin
if(en='1')then
a<=a+1;
c<=a/10; ---49
end if;
end process;
end Behavioral;
The synthesis has given you the answer. Xilinx doesnt support the divide operator when it cannot create a constant value or place a bit shift (as A/2^N is a bit shift).
You need to use the divider IP core.
Also: why is a an inout? A cannot be an inout because integer is not a resolved type, so your code is illegal.
You will need an LCD driver. I suggest reading up on the datasheet for the LCD module. A reference design that may have shipped with the board should show the LCD working.