so what should I do for symmetric output? should I apply another source to M2 gate? in this case which source should vary for calculating linearity range?
What software did you use?
I tried your idea in hspice and I received this error: **error** inductor/voltage source loop found containing 0:vdc1 defined in subckt 0
this is new code:
Vdc1 1 6 0
vcm 6 0 3
VCC 11 0 DC 5
VDD 12 0 DC -5
M1 3 1 5 5 NMOS1 w=10u l=.1u
M2 4 7 5 5 NMOS1 w=10u l=.1u
RC1 11 3 1k
RC2 11 4 1k
RE 5 12 7.2K
E1 1 6 6 7 1
.MODEL NMOS1 Nmos level=2
.print dc id(m1) id(m2)
.dc vdc1 -3000m 3000m 1m
Hi ahmad1954,
just for a better understanding of the differential pair:
Your output characteristics would exhibit better symmetry - even if you apply one single input voltage only - if you reduce the common mode gain by increasing the common emitter resistance.
An ideal diff. pair has a current source in the emitter path (resistance approaching infinite) with a nearly ideal common mode rejection ratio and symmetrical output curves.
For a differential pair I would have thought you would want diff(Id1-Id2)/diff(Vg1-Vg2) but it depends on what your objective is. Your syntax might be slightly different to mine (DERIV for HSPICE I think). I don't see any strange discontinuities doing that and the gm tails off rather than making an abrupt drop to zero which is what yours seems to do.