Problem with DC timing path code

[zyphor]

About DC timing path

Startpoint: clk (clock source 'clk')
Endpoint: ram
(rising edge-triggered flip-flop clocked by clk)
Path Group: clk
Path Type: max

Des/Clust/Port Wire Load Model Library
------------------------------------------------
xx xxx xx

Point Incr Path
--------------------------------------------------------------------------
clock clk (rise edge) 0.00 0.00
clk (in) 1031.00 # 1031.00 r
ram/CLKA (ram) 0.00 # 1031.00 r
data arrival time 1031.00

clock clk (rise edge) 7.40 7.40
clock network delay (ideal) 0.00 7.40
clock uncertainty -0.40 7.00
ram/CLKB (sf_ic_chram) 0.00 7.00 r
library setup time -1.53 5.47
data required time 5.47
--------------------------------------------------------------------------
data required time 5.47
data arrival time -1031.00
--------------------------------------------------------------------------
slack (VIOLATED) -1025.53

who can tell me why DC think the clock source "clk" is a timing path 's startpoint? Actually clk is connected to CLKA and CLKB.

 

[linuxluo]

Re: About DC timing path

hi,
in fact, dc calculate the timing by start with a clk point.
I think maybe you forget set the clock ideal net. so the load of the clock is very big so that the delay time is so big.