*d latch
vd d 0 dc 1
ve e 0 dc 1
*inverter
m17 out d vdd vdd pmos l=0.18u w=0.72u
m18 out d 0 0 nmos l=0.18u w=0.36u
vdd vdd 0 dc 1
*and1 gate
m19 nand1 out vdd vdd pmos l=0.18u w=0.72u
m20 nand1 e vdd vdd pmos l=0.18u w=0.72u
m21 c out nand1 0 nmos l=0.18u w=0.36u
m22 c e 0 0 nmos l=0.18u w=0.36u
m23 and1 nand1 vdd vdd pmos l=0.18u w=0.72u
m24 and1 nand1 0 0 nmos l=0.18u w=0.36u
*and2 gate
m25 nand2 e vdd vdd pmos l=0.18u w=0.72u
m26 nand2 d vdd vdd pmos l=0.18u w=0.72u
m27 c1 e nand2 0 nmos l=0.18u w=0.36u
m28 c1 d 0 0 nmos l=0.18u w=0.36u
m29 and2 nand2 vdd vdd pmos l=0.18u w=0.72u
m30 and2 nand2 0 0 nmos l=0.18u w=0.36u
*nor1 gate
m31 c2 and1 vdd vdd pmos l=0.18u w=0.72u
m32 c2 qb q 0 pmos l=0.18u w=0.72u
m33 q and1 0 0 nmos l=0.18u w=0.36u
m34 q qb 0 0 nmos l=0.18u w=0.36u
*nor2 gate
m35 c3 q vdd vdd pmos l=0.18u w=0.72u
m36 c3 and2 qb 0 pmos l=0.18u w=0.72u
m37 qb q 0 0 nmos l=0.18u w=0.36u
m38 qb and2 0 0 nmos l=0.18u w=0.36u
*display
.tran 1n 10n
.probe
.MODEL NMOS NMOS
+ LEVEL = 3
+ VTO = 0.41
+ TOX = 2.2E-09
+ NSUB = 2.0E+18
+ NFS = 6.0E+12
+ XJ = 6E-8
+ LD = 9e-9
+ UO = 390
+ VMAX = 2.2E+05
+ THETA = 0.80
+ ETA = 2.8E-03
+ KAPPA = 0.2
+ GAMMA = 0.40
+ RSH = 500
+ CGSO = 3.33449e-10
+ CGDO = 3.33449e-10
+ CGBO = 0.0
+ CJ = 4.96491e-3
+ CJSW = 2.45744e-10
.MODEL PMOS PMOS
+ LEVEL = 3
+ VTO = -0.41
+ TOX = 2.2E-09
+ NSUB = 2.0E+18
+ NFS = 6.0E+12
+ XJ = 6E-8
+ LD = 9e-9
+ UO = 175
+ VMAX = 1.1E+05
+ THETA = 0.80
+ ETA = 2.8E-03
+ KAPPA = 0.2
+ GAMMA = 0.40
+ RSH = 500
+ CGSO = 3.33449e-10
+ CGDO = 3.33449e-10
+ CGBO = 0.0
+ CJ = 4.96491e-3
+ CJSW = 2.45744e-10
.end