Problem with crc routine for PCIe

hi,
anyone coded ecrc block used in PCIe?

crc

https://www.easics.com/webtools/crctool

use this website to generate code in either verilog or vhdl to implement crc.

some more posts where crc is discussed

Re: crc

hi,
thanks for the pointers...

i did create a crc routine..
now the problem is when i send data padded with the crc the receiver is reporting a crc error.

how do i debug this?

i am kind of stuck...

Re: crc

Could it be that the receiver just uses another crc algorithm (different polynomial or additional parameters)?

You have to analyze data with known correct crc to find out the used algorithm. of course it may be also an error in implementation. You can use one of the web crc calculators e. g. linked at wikipedia to check your crc results.

crc

Assuming that you have a data width of 32 in the transmitter and another 8 bits of crc bits padded, can you tell me how you are doing the checking on the receiver side?

Re: crc

hi sree,
here 32 bit crc is used for a data width of 32.

I use a protected code at the receiver side.So i have no visibility.

But this has to comply with the spec hence i guess the problem has to be at my end.

Meaning the way i generate the crc ( i am coding it with respect to the SPEC too).

So just need to debug my code and not sure of a better way to do this.

Added after 46 minutes:

basically i am looking for ecrc/lcrc check for PCIe...

Re: crc

If you feel that the problem might be at your end, have u checked the parallel crc encoder circuit that you are using with a serial LFSR ? if i'm not mistaken, it'll take the same number of clock cycles as the degree of ur polynomial

if u want to, i can post the serial crc code if u provide the polynomial

Re: crc

hi,
i use the 32 bit crc whose polynomial is 04c11db7

crc

module crc (clk,reset,din,checksum);

input clk,reset;
input din;
output [31:0] checksum;

wire [31:0] checksum;

reg [31:0] acc;


always@(posedge clk or negedge reset)
if(!reset)
acc <= 32'b0;
else
begin
acc[0] <= acc[31] ^ din;
acc[1] <= acc[0] ^ acc[31] ^ din;
acc[2] <= acc[1] ^ acc[31] ^ din;
acc[3] <= acc[2];
acc[4] <= acc[3] ^ acc[31] ^ din;
acc[5] <= acc[4] ^ acc[31] ^ din;
acc[6] <= acc[5];
acc[7] <= acc[6] ^ acc[31] ^ din;
acc[8] <= acc[7] ^ acc[31] ^ din;
acc[9] <= acc[8];
acc[10] <= acc[9] ^ acc[31] ^ din;
acc[11] <= acc[10] ^ acc[31] ^ din;
acc[12] <= acc[11] ^ acc[31] ^ din;
acc[13] <= acc[12];
acc[14] <= acc[13];
acc[15] <= acc[14];
acc[16] <= acc[15] ^ acc[31] ^ din;
acc[17] <= acc[16];
acc[18] <= acc[17];
acc[19] <= acc[18];
acc[20] <= acc[19];
acc[21] <= acc[20] ^ acc[31] ^ din;
acc[22] <= acc[21] ^ acc[31] ^ din;
acc[23] <= acc[22];
acc[24] <= acc[23];
acc[25] <= acc[24] ^ acc[31] ^ din;
acc[26] <= acc[25];
acc[27] <= acc[26];
acc[28] <= acc[27];
acc[29] <= acc[28];
acc[30] <= acc[29];
acc[31] <= acc[30];
end

assign checksum = acc;

endmodule

give serial input data and check after 27 clock pulses and let me know if it works.
hope i'm not wrong

Re: crc

hi sree,
tried this but i am still not sure...just new to design..
can u post ur testbench for this...

thanks!

Re: crc

There is an online tool that can generate CRC Verilog or VHDL code. It's on http://outputlogic.com

Hope it helps

crc

there is a VHDL code for crc here.. hope this helps.. you can just edit the body of the code to suit for your application...
https://vhdlguru.blogspot.com/2010/03/vhdl-coding-method-for-cyclic.html