problem with constraint file in ise

[ashishjindal76]

hi guys

i have a simple proble. in my design given below
module counter(in,reset,out);

input in,reset;
output [6:0] out;
reg [6:0] out;
reg [3:0] count;

always@(posedge in)
if(~reset)
case (count)
0: if(in) out<=7'b0000001;
1: if(in) out<=7'b1001111;
2: if(in) out<=7'b0010010;
3: if(in) out<=7'b0000110;
4: if(in) out<=7'b1001100;
5: if(in) out<=7'b0100100;
6: if(in) out<=7'b1100000;
7: if(in) out<=7'b0001111;
8: if(in) out<=7'b0000000;
9: if(in) out<=7'b0001100;
10: if(in) out<=7'b0000001;
11: if(in) out<=7'b1100000;
12: if(in) out<=7'b0110001;
13: if(in) out<=7'b1100000;
14: if(in) out<=7'b0110000;
15: if(in) out<=7'b0111000;

default: if(in) out<=7'b0;
endcase

this design gets synthesised in ise5.2 without errors but the problem comes when i want to apply the constraint file. when the pins or the ports to be configured it doesnot show the input ports. can anyone tell me what could be the possible error and the solution to it.

thx in advance.

regards
Ashish