[SOLVED] problem with conditional operator in verilog

arishsu · Sep 11, 2013

Is this syntax is right for 4:1 mux output?

assign Y=(S==0x)?((S==00)? I[0]:I[1])((S==1x)?((S==10)? I[2]:I[3]));

S is 2 bit reg(select line), I is 4 bit reg(input) and Y output.

mrflibble · Sep 11, 2013

Best get rid of the x don't cares. See this thread for some examples.

Personally I use something like this:

Code:

assign o= (s[0]==0)?((s[1]==0)?i[0]:i[1]):((s[1]==0)?i[2]:i[3]);

arishsu · Sep 11, 2013

Thank you..

ads-ee · Sep 11, 2013

mrflibble said:
Best get rid of the x don't cares. See this thread for some examples.

Personally I use something like this:

Code:

assign o= (s[0]==0)?((s[1]==0)?i[0]:i[1]):((s[1]==0)?i[2]:i[3]);

A little formatting might make it more readable...

Code Verilog - [expand]
1
2
3
4
assign o = (s[0]==0) ? ([s[1]==0) ? i[0]   // 00
                                  : i[1])  // 10
                     : ((s[1]==0) ? i[2]   // 01
                                  : i[3]); // 11

mrflibble · Sep 12, 2013

ads-ee said:
A little formatting might make it more readable...

Fully agreed. I was just reciprocating laziness, and as such did a quick copy/paste from that other thread with the kind of code snippet I'd use.

[SOLVED] problem with conditional operator in verilog

arishsu

Member level 3

mrflibble

Advanced Member level 5

arishsu

Mohammed_Verification

arishsu

Member level 3

ads-ee

Super Moderator

mrflibble

arishsu

mrflibble

Advanced Member level 5

Similar threads

Code Verilog - [expand]
1 2 3 4	assign o = (s[0]==0) ? ([s[1]==0) ? i[0] // 00 : i[1]) // 10 : ((s[1]==0) ? i[2] // 01 : i[3]); // 11

[SOLVED] problem with conditional operator in verilog

Member level 3

Advanced Member level 5

Member level 3

Super Moderator

Advanced Member level 5

Similar threads

Privacy & Transparency

Privacy & Transparency