[SOLVED] problem with clock controlled multiplexer (vhdl)

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Nick Ostro

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hello everyone,i am currently working on a multistage interpolator x2,so i need to create a multiplexer controlled by the clock of my design.i want the multiplexer to give input a(in_a) when the clock rises and input b when the clock falls.i have written the following code(which works in modelsim)

Code: 
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
use ieee.std_logic_unsigned.all;

entity muxaki is
    Port ( in_a : in  signed (15 downto 0);
           in_b : in  signed (15 downto 0);
           clk : in  STD_LOGIC;
--           clk_aplo_dia2 : in  STD_LOGIC;
           mux_out : out  signed (15 downto 0));
end muxaki;

architecture Behavioral of muxaki is

SIGNAL not_clk: STD_LOGIC;

begin

process (clk,not_clk) 

          begin
          if rising_edge(clk) then
             mux_out <=in_a;
           elsif rising_edge(not_clk) then
           mux_out <=in_b;  
			end if;	
				 
 end process;
				 
				 
not_clk<=not(clk);

end Behavioral;

but in xilinx gives the following message:

WARNING:Xst:647 - Input <in_b> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.


.any ideas?
 

You cannot have a dual clock edge triggered register in an FPGA, so this is never going to work like this. Are you sure you dont need to oversample the "clock" and detect the edges with logic?

The error you get is probably because you left in_b unconnected, so it didnt complain about dual clock edges.
 
thank you for your interest!
what do you mean when you say tha in_b is unconnected?havent i connected it with mux_out inside the process?also i am not familiar with clock oversampling,i will research about it! is there any other way to get the job done?
 

I dont know where clk and not_clk are coming from. And in_b is probably unconnected outside this block - so you didnt connect it to anything externally.
 

i have made the multiplexer top module(so the code i paste,is the only code to compile)to synthesize it indepedently, so the warning comes from the particular component.
clk is the clock input and in the end of the code i assign not_clk=not(clk);
 

No matter how you connect "not_clk", the code isn't synthesizable. You can't have a register operating on both edges or two different clocks. The multiplexer can be only implemented in a combinatorial process, optionally the input signals can be registered on either edge before going to the MUX. This is a regular DDR input register functionalilry, you can use a low level primitive for it.
 
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