UPDATE:----
I wanted to check if my entire ahb bus arbiter logic itself is correct first. So what I did was I created a skeletal ahb arbiter verilog code by stripping off all the control signals such as hresp, htrans, hburst etc from the code and also removing the split operation, bus idle check etc. Then I wrote a basic testbench in the same manner in which I had coded the testbench previously as you can see on this thread.
And surprise! It works. All the grant signals occur correctly upon asserting the requests and get deasserted upon deasserting the requests.
So the problem comes when I add those whole bunch of control signals and a bunch of nested if else conditions which is kind of inevitable if they were to be included in the code. That is when the grant signals fail to get asserted.
I am enclosing the simplified arbiter code again in this thread so that you guys can compare this and my original code to spot what may be the changes that can be made to the original complex code to make it work.