samiran_dam
Full Member level 2
Hi,
Below are the details of my system configuration:
Platform: Cent OS 5.8 (Final) [64 bit]
IC version: IC 6.1.4 (Open Access [OA] version) [64 bit]
Assura version: Assura-614
Technology: UMC180_analog [64bit]
I have set my cds.lib, .cdsinit and .basrc files as follow:
cds.lib
.cdsinit
.bashrc
assura_tech.lib
Using Schematic XL, I have created a simple inverter and did a transient analysis using ADE (G)XL. It worked fine. Then I did the layout using Layout XL. But in DRC form (opened from the Assura>Run DRC option), when I tried to run DRC, I gor the following error:
"Failed to build VDB. Cannot submit DRC Run."
When I checked cds.log for more information about the error I see,
*Error* load: can't access file - "/designPackages/umc_installer/UMC_64bit/UMC180_Analog/Designkits/Cadence_6.1/RuleDecks/Assura/DRC/G-DF-LOGIC18-1.8V-3.3V-1P6M-Assura-drc-memory.rul"
Errors exist in the rules file '/software/designPackages/UMC_64bit/UMC180_Analog/Designkits/Cadence_6.1/RuleDecks/Assura/./DRC/G-DF-MIXEDMODE_RFCMOS18-1.8V-3.3V-1P6M-MMC-Assura-drc-2.10-p1.rul'.
From this, error log I can understand that there are no such files and I checked that to be true. I wonder from where this files could be pointed, I could not figure that out anywhere in my configuration files [all the paths given in those configuration files (cds.lib, .cdsinit, .bashrc, assura_tech.lib) are valid - I have checked that].
Please help to resolve this issue.
Regards
Sam
Below are the details of my system configuration:
Platform: Cent OS 5.8 (Final) [64 bit]
IC version: IC 6.1.4 (Open Access [OA] version) [64 bit]
Assura version: Assura-614
Technology: UMC180_analog [64bit]
I have set my cds.lib, .cdsinit and .basrc files as follow:
cds.lib
Code:
######################## TECHNOLOGY LIBRARY ########################
INCLUDE /software/cadence/IC614/share/cdssetup/cds.lib
DEFINE UMC_18_CMOS /software/designPackages/UMC_64bit/UMC180_Analog/Designkits/Cadence_6.1/UMC_18_CMOS
DEFINE avTech /software/cadence/ASSURA/tools/assura/etc/avtech/avTech
######################## USER LIBRARY ########################
DEFINE myLib /work/myLib.cdsinit
Code:
load("/software/cadence/IC614/tools/dfII/samples/local/schBindKeys.il")
load("/software/cadence/IC614/tools/dfII/samples/local/leBindKeys.il")
load("/software/cadence/IC614/tools/dfII/samples/local/leConfig.il")
load("/software/cadence/IC614/tools/dfII/samples/local/awvBindKeys.il")
load("/software/cadence/IC614/tools/dfII/samples/local/leSchBindKeys.il")
load("/software/cadence/IC614/tools/dfII/samples/local/aaConfig.il")
load("/software/cadence/IC614/tools/dfII/samples/local/lxBindKeys.il")
load("/software/cadence/ASSURA/tools/dfII/samples/local/uiConfig.il")
load("/software/cadence/IC614/tools/dfII/samples/local/leConfig.il")
load("/software/cadence/IC614/tools/dfII/samples/local/metConfig.il")
load("/software/cadence/IC614/tools/dfII/samples/local/mspsBindKeys.il").bashrc
Code:
# .bashrc
# Source global definitions
if [ -f /etc/bashrc ]; then
. /etc/bashrc
fi
# User specific aliases and functions
export CDS_AUTO_64BIT="ALL"
export CADENCE_HOME="/software/cadence"
export PATH="$CADENCE_HOME/IUS/tools/bin:$PATH"
export PATH="$CADENCE_HOME/IUS/tools/simvision/bin:$PATH"
export CDSHOME=$CADENCE_HOME/IC614
export OAINST=CDSHOME
export CDS_SITE=$CADENCE_HOME/IC614/share
export PATH="$CADENCE_HOME/IC614/tools/bin:$PATH"
export PATH="$CADENCE_HOME/IC614/tools/dfII/bin:$PATH"
export QRC_HOME=$CADENCE_HOME/EXT
export PATH="$QRC_HOME/bin:$PATH"
export QRC_ENABLE_EXTRACTION="t"
export ASSURAHOME=$CADENCE_HOME/ASSURA
export PATH="$CADENCE_HOME/ASSURA/tools/assura/bin:$PATH"
export PATH="$CADENCE_HOME/MMSIM/tools/bin:$PATH"
export PATH="$CADENCE_HOME/MMSIM/tools/dfII/bin:$PATH"
export CDS_Netlisting_Mode="Analog"
export RET_DISABLE="TRUE"
export SPECTRE_DEFAULTS=" +savestate"
export CDS_LIC_QA_TesT="./license.log"
export LD_LIBRARY_PATH="$CADENCE_HOME/IUS/tools/lib:$CADENCE_HOME/IUS/tools/dfII/lib:$CADENCE_HOME/IC614/tools/lib:$CADENCE_HOME/IC614/tools/dfII/lib:$CADENCE_HOME/MMSIM/tools/lib:$CADENCE_HOME/MMSIM/tools/dfII/lib:$CADENCE_HOME/IUS/tools/verilog/lib:$LD_LIBRARY_PATH"
export LM_LICENSE_FILE=[COLOR="#0000FF"]<license_server_ip>[/COLOR]assura_tech.lib
Code:
DEFINE UMC_18_CMOS /software/designPackages/UMC_64bit/UMC180_Analog/Designkits/Cadence_6.1/RuleDecks/AssuraUsing Schematic XL, I have created a simple inverter and did a transient analysis using ADE (G)XL. It worked fine. Then I did the layout using Layout XL. But in DRC form (opened from the Assura>Run DRC option), when I tried to run DRC, I gor the following error:
"Failed to build VDB. Cannot submit DRC Run."
When I checked cds.log for more information about the error I see,
*Error* load: can't access file - "/designPackages/umc_installer/UMC_64bit/UMC180_Analog/Designkits/Cadence_6.1/RuleDecks/Assura/DRC/G-DF-LOGIC18-1.8V-3.3V-1P6M-Assura-drc-memory.rul"
Errors exist in the rules file '/software/designPackages/UMC_64bit/UMC180_Analog/Designkits/Cadence_6.1/RuleDecks/Assura/./DRC/G-DF-MIXEDMODE_RFCMOS18-1.8V-3.3V-1P6M-MMC-Assura-drc-2.10-p1.rul'.
From this, error log I can understand that there are no such files and I checked that to be true. I wonder from where this files could be pointed, I could not figure that out anywhere in my configuration files [all the paths given in those configuration files (cds.lib, .cdsinit, .bashrc, assura_tech.lib) are valid - I have checked that].
Please help to resolve this issue.
Regards
Sam