[SOLVED] Problem with array of register.

Hi everybody!!
I have a stuck to compare a portion of bytes of two registers.
I have a 2 register with 20 byts of width. The value of 1st registers always changes by loop. I want to compare only some portion of two register(let it be 64 bit, 8byte). But the length of comparing bits is variable(can change value). If i use a loop variable in indeces, the bag accur as it is a not a constant.
In this case i want to use only first 63 bits. Now "pattlen = 63"

I cant use bit-slice as the right site should be constant

You'll have a another iteration loop that performs a bit-wise compare.

It should be noted that if the code is intended for synthesis, the variable length compare translates to a huge amount of combinatorial logic.

Lopps in Verilog and VHDL represent replication spacially, which is not the same as a temporal repeatition. Hence, loops when synthsized into logic or elaborated for simulation must have a constant for the number of itterations.

Ask yourself hoow can this circuit be realized if the circuit has to change the amount of logic that exists on the fly?

This is the saame reason you can't use a varable width for a bitslice as it implies dynamically generated logic.

Another observation is you seem to be trying to decode some state variable in an initial block. Initial blocks are only executeed once at time 0. As your state machine can't execute in 0 ns, that if compare will fail and none of the for loop logic will used.

You have to step back and not attempt to implement this as a software program, but think of what hardware logic gates and registers you need.

Thank you gays all of you!!
I solve the problem with bitwise operation.
if ((buffpatt & buffshift) == buffpatt)
then
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