problems with .drl file altium
1. Only the fab knows the exact dielectric constant for the batch of material they will use to make your board. You tell the fab what impedance you are targeting, and they make use of the data included with the dielectric to make small adjustments in the trace width to achieve the desired impedance. Many fabs, especially the better ones, have Polar field solvers they use to calculate layer-by-layer impedance for the desired stackup. That's what they use to adjust your traces. The better fabs also provide TDR verification of impedance for the finished board, so you know that you got what you asked for.
2. Artmaster probably refers to a Gerber drawing. Where did you see it?
3. Layer numbering in copper is normally only done for coupons to verify stackup. There is no standard. If you use layer numbers, you want them to be visble when holding the board up to light so you can verify the stackup order yourself. Plane layers are negative layers, so a window needs to be provided in the copper for plane layers. Since you are viewing the numbers by looking through the board from one side, the bottom number is the only one that needs to be reversed - it will appear backwards when you look at the bottom of the board, but normal if you look through the board.
4. No, PADS and Allegro do not display the net name the same way as Altium Designer. You can get a status line display of the netname, but you don't see the netname in text on the objects in the layout window.