intermediate status unrouted
You still have over 2000 nets that are unrouted after 15 hours. Either the FPGA is out of resources, the placement that it picked is unroutable, or the extra unit you added has a very large amount of logic.
In the Place and Route properties box, you can change a couple of properties. For testing purposes, choose a low effort level and re-run the design. It should finish more quickly, but will not meet timing. If it finishes at all, then you know the design will fit and is routable.
Next, increase the effort level, and vary the placer cost table value. This varies the algorithm it uses to place the logic. For the type of designs we do, "10" seems to be a good seed value. However, other FPGAs and other types of designs will work better with other numbers. Try varying this to see which is better. You can also enable mutipass routing and have the tools cycle through a range of seed values keeping only the top few designs.
Finally, Xilinx tools are memory hogs. How much ram is installed in your machine? Less than 1 gig, can cause problems. The Xilinx tools can only optimize the amount of logic that it can hold in ram. If the design is larger than it can fit into available ram, the optimizer goes wonky and only optimizes in chunks.
Check your total ram usage in the reports from your last successful run. If this is close to the limit in the machine, then your additional unit has pushed you over the edge and you need more ram.
--- Steve
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