Problem while simulating the following code for memory

[RAVINDRA SINGH]

HELLO EVERYONE

THIS CODE OF MINE IS NOT WORKING PROPERLY ; CAN ANY1 SUGGEST WHAT IS THE PROBLEM WITH EXPLANATION AND ALSO THE REMEDY FOR IT. SUPPOSE WE INPUT(WRITE) 3 DIFFERENT DATA SAY x, y, z AT THREE DIFFERENT LOCATIONS: SAY LOCATION 0 ,1 ,2. NOW IF I WANT TO READ DATA AT LOCATION 0 , THIS CODE IS WRITING THE LAST INPUT DATA AT THIS LOCATION i.e AT LOCATION 0 WHICH IS z AND ALSO AT THE OUTPUT IT READS AS z WHEREAS IT SHOULD BE x. CAN ANYONE EXPLAIN THE REASON AND LOGIC BEHIND IT. here is the code:

library IEEE; -- rtl schematic not working although the outer block is visible.
use IEEE.STD_LOGIC_1164.ALL; -- for address more than 5 bits as itz taking too too long.
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
USE WORK.UP_PACK.ALL;

entity memory_rw is
Port ( MS : in std_logic; -- MEMORY SELECT
MR : in std_logic; -- MEMORY READ
MW : in std_logic; -- MEMORY WRITE
M_IO: IN STD_LOGIC; -- W/R MEMORY FROM UP OR WRITE A PROGRAM IN MEMORY FROM IO.
--PRG_BEGIN: IN INTEGER; --PRG_END: IN INTEGER; --MRA : in std_logic_vector(7 downto 0);
MRWA : in std_logic_vector(4 downto 0); -- MEM READ/WRITE ADDRESS
MDI : in std_logic_vector(7 downto 0); -- MEM DATA IN
MDO : OUT std_logic_vector(7 downto 0)); -- MEM DATA OUT
end memory_rw;

architecture MEM_ARCH of memory_rw is
SIGNAL M_STATUS:STD_LOGIC_VECTOR(3 DOWNTO 0):= "ZZZZ";
signal mem_sig : mem_array;
begin
M_STATUS<= MS & M_IO & MR & MW; --mem select, mem/io, mem read, mem write.
--MEM/IO = 0 - UP AND MEM; 1 - EXTERNAL AND MEM.
PROCESS(M_STATUS,MRWA)
VARIABLE MEM : MEM_ARRAY;
VARIABLE M_INT : INTEGER;
BEGIN
CASE M_STATUS IS

WHEN "1001" => M_INT:= CONV_INTEGER(MRWA);
mem_sig(m_int)<=mdi;
--MEM(M_INT):= MDI; ----- WRITING A DATA FROM THE UP INTO THE MEMORY
MDO<="ZZZZZZZZ";

WHEN "1101" =>M_INT:= CONV_INTEGER(MRWA); ----- WRITING A PROGRAM IN THE MEMORY from user.
mem_sig(m_int)<=mdi;--MEM(M_INT) := MDI;
MDO<="ZZZZZZZZ";

WHEN "1010" => M_INT:= CONV_INTEGER(MRWA);
mdo<=mem_sig(m_int);
--MDO<= MEM(M_INT); ----READING A DATA FROM A MEMORY LOCATION FOR UP

WHEN "1110" => M_INT:= CONV_INTEGER(MRWA);
mdo<=mem_sig(m_int);
-- MDO<= MEM(M_INT); ---READING A DATA FROM A MEMORY LOCATION FOR EXTERNAL DEVICE.

WHEN OTHERS => MDO <= "ZZZZZZZZ";

END CASE;
END PROCESS;


end MEM_ARCH;


:?:

 

[lucbra]

If I understood the problem, you want to build an address decoder for a microprocessor, so that it can access several banks of data?

Where is the read/write signal or an enable?
these signals typically help in synchronizing the decoder with your data stream.

If you want more replies on your topic, just post your problem in the forum not in the VHDL group

regards

PS use lower case characters to write, not UPPER CASE - as it looks like you are shouting