PROBLEM SYNTHESISING THE CODE in VHDL

Hi

I am writing a code for Matrix Transpose in VHDL i am taking input in row major and one element of matrix per every clock cycle and i store the data in column major format after that i send tha data in coloumn major format element by element every clock cycle to the output . The code is as below it is simulating properly but the post synthesis results are not right can anyone plz help how to synthesize code to get correct results

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.numeric_std.ALL;

entity Matrix_Trans_Sysgen is
generic(n: integer :=3);
port (my_clk : in std_logic;
my_ce : in std_logic;
input_matrix : in std_logic_vector(5 downto 0);
output_matrix : out std_logic_vector(5 downto 0)
);
end Matrix_Trans_Sysgen;

architecture Behavioral of Matrix_Trans_Sysgen is

type t1 is array (natural range<>) of std_logic_vector(5 downto 0);

signal a : t1((n*n)-1 downto 0) :=(others => (others =>'0'));

signal output_there : std_logic :='0';

signal x : integer range 0 to 2*n :=0;
signal y : integer range 0 to 2*n :=0;
signal z : integer range 0 to 2*n*n :=0;

begin

----- Process to take all input_matrix into array
process(my_clk,input_matrix,x,y)
begin

if(x < n) then
if(y < n) then
if(rising_edge(my_clk)) then
a(y*n+x) <= input_matrix;
y <= y+1;
end if;
else
x<=x+1;
y<=0;
end if;
else
output_there <= '1';
end if;

end process;


----- Process to send all output elements through port
process(my_clk,z,output_there)
begin

if (output_there = '1') then
if(z < n*n) then
if(rising_edge(my_clk)) then
output_matrix <= a(z);
z<=z+1;
end if;
end if;
end if;

end process;

end Behavioral;

Thanks and Regards
Teja

Hi tejakr2002,

Can you share the error during the synthesis?

I think you need to use the if(rising_edge(my_clk)) then before the other two if statement.
Otherwise the problem is that the first else part onwards it wont sync with the my_clk, because the if(rising_edge(my_clk)) then is closed with the end if; statements.

Better you can share the error.